Pspice simulation of diode reverse leakage current

I need to vary (with the dev statement) the reverse leakage current of a diode in order to do Worst Case Analysis simulations.The problem is I can`t find the parameter that controls that current. I know it has something to do with Isr and NR, but they don=B4t affect it directly and I have no idea of how they interact in order to model the leakage current. I wasn=B4t able to find a good explanation either on the spice manual provided by Cadence or on the internet. If someone can shed a light on this problem I would be more than grateful.

Martin Sigwald

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Martin Sigwald
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Try varing the IS which is suppose to be the reserve saturation current. I believe a read that in spice. Vbe from 0 to breakdown is modeled or assumed to IS. Try chaning IS.

Robert

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rbolanos

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