Programmable pulse generator.

Sounds good to me.

DNA

I get pulses down to 200 ns from a PIC, but the step size is in 200 ns increments.

Check out the source code and schematic for MAX038 signal generator...

Luhan

Maxim doesn't sell the MAX038 anymore.

--
Bill Sloman, Nijmegen

--
The way I'd do it would be with BCD switches, some glue logic, and 
two programmable decade down-counter chains,  one to generate the 
pulses and one to generate the rep rate. 

The problem that comes up, however is that a width of  "several 100 
µs" won't allow you to get rep rates in the 10's of kHz because one 
pulse won't have ended by the time another one is supposed to start. 

What can you live with, realistically?

The pulse generation in this circuit does not use it. A single line from the PIC is buffered and routed to an output.

Luhan

I'm mostly interested in pulse widths ranging from 100ns to 1000ns, larger pulse widths would be nice but not essential. Also, rep rates from 1 to 20kHz would be fine.

The reason I thought about using a dds is that it will give me a good resolution, I'd like to be able to increase the pulse width in 10ns increments. I had thought about simply using the Pic to toggle a pin but the instruction cycle is 200ns so I could only increase in 200ns steps.

Cheers,

JW

___

Might have trouble using a PIC to generate the pulse here. Most PICs execute a non-branching instruction every 4th pulse of the system clock. System clocks up to and including the 16F series are 4-20 MHz. So to have the PIC execute something like

bsf PORTA, 0 bcf PORTA, 0

Has already put a minimum pulse width on the system of 2 instruction cycles, 8 machine cycles, or 8/20000000 seconds, or 400 nanoseconds.

Even using one of the 18Fs at 40 MHz only gets you down to a 200 ns pulse width. Pulse width accuracy and stability would of course be subject to crystal specs, temp, aging, etc.

If you could live with this, you could generate an interrupt from the timers in the PIC on an overflow basis to call the interrupt on a KHz-long duty cycle.

When you say "rep rate" do you mean one pulse that repeats itself every period of the "rep rate" or burst pulse of n reps of the same pulse(we'll need a duty cycle then).

10nsec increments implies a 100MHz clock, which you can buy of the shelf from Farnell -order code 329-8504 for 26.53 euro. The same range includes a 125MHz clock for the same money.

The synchronous counter you need to increment the pulse width in 10nsec steps is a bit more tricky - as far as I know, no flavour of TTL or CMOS will let you put together an eight-bit counter that is guaranteed to count at 100MHz.

I'm fairly confident that you would be able to program any one of a number of programmable logic devices to work as a 100MHz or 125MHz

8-bit wide (or wider) synchronous counter - the Lattice LC4032 might be worth looking at, or the Altera EPM3032 or something out of the Xilinx CoolRunner range -

Somebody on comp.arch.fpga could probably give you chapter and verse.

If you were to go for ECL, you wouldn't stop at 100MHz - Vectron will sell you a 500MHz crystal oscillator (for something closer to $100 when I last asked, some ten years ago) and MC100E016 eight-bit synchronous counters

can be assembled to give synchronous counters of arbitrary width counting at 500MHz.

And you need not stop at 2nsec pulse widht increments - the MC100E195 can provide at least 2nsec of programmable variation in propagation delay, controlled by a 7-bit word - roughly 20psec increments..

Unless you do want spectacular accuracy, you would probably be better off making a 74121 monostable programmable, by replacing the external timing resistor with a programmable current source - probably a current mirror built with the two matched PNP transistors in a CA3096. The HFA3096 looks as it if would be even nicer

if you could find someone who sold it.

It is a long time since I saw a schematic for the internals of the

74121, but IIRR a current variation from about 2mA down to about 200uA would give you the 10:1 range you ask for with a timning capacitance around 22pF (which has to include the collector capacitance of the PNP transistor acting as your current source).

In a similar application, working with the ECL MC10198 monostable, I further extended the range by switching in extra timing capacitors with SD214 MOSFET transistors - when they were off these transistors only looked like a couple of pF, and the on resistance was around 50R, which didn't mess up the monostable too badly. Colleagues who tried other switches didn't do as well.

--=20 Bill Sloman, Nijmegen

Hi Charles,

When I say rep. rate I mean the rate at which the single pulse repeats. So a single 100ns pulse would be generated every 200us if the rep rate was 5kHz.

I gave up on the idea of using the Pic to generate the short pulse for the reason you mention. My 20Mhz 16F877 has no chance of producing

100ns pulses that can be incremented in 10ns steps. Using a DDS I'm hoping to achieve this relatively easily. I've got some samples from Analog Devices, the AD9833 is good for 12.5MHz and has an accuracy of 0.1Hz. For my application I need a min. of 100ns (so a 5MHz square wave) and to increase the pulse width to 110ns I could lower the frequency to 4.545MHz.

I'm reasonably confident that the Pic & DDS approach will suffice for now, but have no idea about how to get a single pulse from the DDS output. I'm hoping to employ some kind of logic, but don't know what!?

Thanks

JW.

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Hi Bill,

Thanks for all the useful info and suggestions, I'm especially keen to experiment with some PLD's and this project could be a nice starting point to get my teeth into them! As for my first attempt, I've already got some DDS samples and have written the code to output the kHz PWM signal. All I have to do now is interface the Pic with the DDS which shouldn't take long once the PCB arrives.

To get the 10ns accuracy I thought the DDS would be sufficient. At 5MHz I will get a pulse width of 100ns (the minimum required), lowering the frequency to 4.5455MHz would give me a 110ns pulse. The resolution of the AD9833 is 0.1hz (when clocked at 25MHz) so I didn't think there would be a problem, I've not tried anything like this before so I could be very wrong.

Assuming all goes to plan and I get the DDS producing a clean square wave that I can increment in 10ns steps, I'm still stuck on how to get a single pulse from the continuous output of the DDS that repeats at the PWM frequency. Do you have any hints on how to achieve this?

Thanks,

JW.

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Start over. The DDS is a fine way of setting up the pulse repetition rate, but pretty much useless for defining the width of a single isolated pulse.

Incidentally, note that you DDS chip doesn't produce a square wave directly, but in fact produces a stepped approximation to a sine wave, which you hve to filter to get rid of the high frequency content at the DDS clock frequency and multiples of the DDS clock frequency. Only after the raw output has been filtered can you stick it into a comparator and hope to get a respectable square wave output (free from the jitter approaching the DDS clock period you'd get if you fed the comparator with the unflitered output).

--=20 Bill Sloman, Nijmegen

--
OK. From another post I understand that you want to be able to vary
the pulse width in 10ns increments, which means that we need,
basically, a 100MHz clock (200MHz would be better) to make the thing
work if you build it with logic.  

TI has a nice TTL part, a CY74FCT191, which will fill the bill for
the pulse generator, but according to TI's web site the currently
available parts are in Europa so, if you're serious, you'd have to
get them from disty there.

What I envision is a chain of three programmable down-counters
clocked at 100Mhz which you can use your µC to control.

The way it would work is that your µC, working invisibly in the
background, would send the "width word" to a 12 bit shift register
sitting on the broadside loads of the counter chain, would load that
value into the counters and would simultaneously set an RS latch and
start the counter.  When the counter timed out and all three of the
counter chain's Terminal Count outputs went true, that would reset
the latch, the result being that the output of the latch would be
the pulse you're looking for.

Your µC would now be doodling along, counting the rep rate time
you'd told it you wanted, and when it got there it'd start the cycle
anew.

Interestingly, since you want 10ns timing increments and that
requires at least a 100MHz clock, you'd be able to get pulses out of
the system starting at 10ns.

If you want to go that route you need to understand that it's not a
trivial undertaking.  I'll be happy to help you out with a schematic
and stuff, but if you're not willing, or able, to do a proper PCB
layout to make sure it'll work right then (no offense intended)
count me out.

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Hi John,

Thanks for the offer of help. I had a look at the CY74FCT191 on the TI website and followed the link to buy samples. The UK distributor is a company called Silica (never heard of them!) and their website has no mention of the part just a link back to the TI website, I'll try phoning them later.

I can get PCB's made up, although I'm at a university and there's a long waiting list, especially as this isn't directly related to my research. The reason I'm doing this is partly because it's a good learning experience in a field I know little about. Also, my group has managed to destroy a couple of expensive pulse generators recently, so a low cost replacement would be handy.

I could buy an Altera 7000 CPLD evaluation board from Farnell for =A399. I've never used anything like it before so it'd be a steep learning curve but I wouldn't need to make a PCB for the time being, plus it's a nice skill to put on the CV. What do you think to this approach?

Thanks,

Jim W.

--
I have no experience with CPLDs, so I can\'t say, sorry.

But, I\'ve come up with a circuit that will let you get single pulses
out of your DDS and set the rep rate with your µC, and I\'ll post a
schematic to abse sometime today.

In article , wrote: [...]

The MAX7000 is a nice CPLD but a little power hungry. The tools from Altara are sort of "okish".

A few pointers:

Before you begin, estimate how many flip-flops you need and then double it and get a CPLD bigger than that. It is nearly imposible to do a CPLD design that gets all the macrocells working. The ability to hook things up is usually the limiting factor.

Remember that the logic equations are always operating. It isn't like a processor where the instruction happen one after another.

Altera's tools have a couple of known bugs. The biggest is that it doesn't do the tri-states right in VHDL. If you code VHDL, use their tri() function not the VHDL standard 'Z'.

Be prepared to have to add a jumper from one of the CPLD outputs to the global chip enable if you do tristates. They didn't provide enough abilities in this department.

The error messages that Quartus makes can be misleading sometimes. If the error message doesn't seem to match the statement it is on, look at the previous statement carefully for a missing semicolon.

RS latches are just fine to do in the MAX7000. Transparent latches can be trouble but they can be made if you really, really, really have to. In other words don't.

The MAX7000, IIRC, is one of the ones with a "turbo bit". If a section needs to go fast, you want to set the "turbo bit". The "turbo bit" could also be called the "draw a lot more Icc" bit too.

When the MAX7000 first powers up, it wakes up stupid and then starts to actually do the logic after a short warm-up period. Make sure you never count on it being right at the start. If you are driving a push-pull stage don't assume that the CPLD will never make PUSH and PULL both high because it may happen briefly at power up.

The MAX7000's current is all drawn in narrow 1 billion amp pulses. Make sure to bypass the heck out of any PCB you do your self.

--
--
kensmith@rahul.net   forging knowledge

This sounds perfect for some of the small to small-medium sized CPLDs and complex FPGAs. easy to get nice digital controls too.

--
JosephKK 
Gegen dummheit kampfen die Gotter Selbst, vergebens.   
--Schiller

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Those DDS are for producing low distortion sine waves at arbitrary frequencies. An Arb generator may be closer to what you are trying to achieve.

--
JosephKK
Gegen dummheit kampfen die Gotter Selbst, vergebens.  
--Schiller

In the past few days I've been playing around with a cpld eval board (altera max emp7128slc84). Never used one before so I'm just getting to grips with the software etc. I've managed to hook up a few flip flops etc and interface with a microprocessor, still have a lot to learn before I'm able to use it to produce a workable pulse generator. Any advice on how to go about implementing such a thing?

I've put the DDS idea on hold until I get a PCB made up, I managed to get hold of the schematic John posted and it looks as though it'll do the trick. Thanks for that!

Cheers,

Jim W.

Try throwing this at Google "altera max epm7128slc84". The results were amazing.

--
 JosephKK
 Gegen dummheit kampfen die Gotter Selbst, vergebens.  
  --Schiller