power supply control

Hi,

I am using an FPGA to control a SMPS, and was thinking that instead of the "standard" PID loop type control, maybe it would be useful to control the power supply using a smarter algorithm. For example if the components in the power supply are known (ie. inductance, capacitance, turns ratios, saturation current limits, V/us limits, etc) and also the power supply currents and voltages are sampled by the FPGA, couldn't formulas be used in the FPGA to control the power supply mathematically rather than using a direct PID type feedback loop? This way the next switch on-time could be mathematically calculated each cycle, not sure how well this would work, as the loads could be variable etc.

cheers, Jamie

Reply to
Jamie Morken
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That doesn't make sense. For the small fraction of the cost of FPGA, you can have the very good DSP designed specifically for the power control applications. Especially if all glue logic and parts like ADCs, EEPROMs etc. are put into the account.

What is not right with the standard PID?

Sure. Whatever algorithm can be done as the software.

You can take all of that into the account.

Software implementation of the smart control would be much simpler and cheaper then doing all of that in the hardware.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

But a PID controller _is_ mathematical.

Yes, you could certainly come up with a controller that took more of the dynamics of the electronics into account, although you'd have to thoroughly understand the electronic behavior of your circuit to make a power supply controller that'll work better, instead of just being an overly elaborate way of working as well as a PID, or worse an overly elaborate way of making smoke.

As Vladimir said, however, you can do this all in a DSP chip these days. Unless you have some terrifically promising algorithm that gets really valuable in a 1MHz switching rate converter and then only if it's executed sample-by-sample, you can do this all with DSP chips.

And by the time your algorithm is ready for market, there'll probably be a DSP chip that can handle _that_ too.

FPGAs are for fast computation, DSP for more moderate speeds, but the line between "fast" and "moderate" keeps getting faster and faster.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" gives you just what it says.
See details at http://www.wescottdesign.com/actfes/actfes.html
Reply to
Tim Wescott

Hi,

Yes it could be done with a DSP, but my ADC/DAC sampling rate is up to

1MHz, (ie. 12bit resolution 20MHz+ SPI clock) and there are actually A LOT of ADC's and DAC's as there is more than 1 SMPS circuit being controlled, also the FPGA has nice predictable and fast response to the overcurrent and overvoltage signals as well as good predictable gate drive PWM. I am using upwards of 200 digital I/O on the FPGA, I might put a soft CPU in the Cyclone 3 FPGA and try that approach, but I think its hard to beat an FPGA for something like this, when you have a lot of fast parallel tasks required.

cheers, Jamie

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Reply to
Jamie Morken

Maybe if you explain more on how your circuit works others might provide more elaborate insights ..?

What SMPS type do you use?

So far the only FPGA benefits I can see so far is the possibility to replace many dedicated DSPs with one fpga in addition to the extra i/o.

Reply to
sky465nm

What would be a good low cost DSP capable of C code implementation of

100kHz PWM of 6 channels with 1MSPS sampling of 4 SPI ADC's (with digital lowpass filtering) and 1MSPS update of 2 SPI DAC's?

I think this would require parallel SPI buses from the DSP, as most SPI ADC's and DAC's that would work for me have max clock rate of 20MHz, unless they are all read sequentially on the same SPI bus I guess..

cheers, Jamie

Reply to
Jamie Morken

oops I mean read concurrently, as in use multiple MISO lines for the ADC's and one common SCLK and CS' for all ADC's.. would require multiple SPI buses still though, or else a software SPI with multiple polled MISO lines, how else could this be done in a DSP with multiple high speed SPI devices?

cheers, Jamie

Reply to
Jamie Morken

Depending on the required amount of processing, I see two possible candidates:

  1. TMS 28xx series
  2. BlackFin 534.

Or, you can probably split the control among two small dsPICs or FreeScales 56xx.

In addition to the SPI (IIRC which can run at ~50 MHz on those), those CPUs have 1 or 2 DSP serial ports which can be configured to SPI mode as well. On BlackFin, the serial port has two data inputs and outputs per port; that is very handy when you have to connect multiple devices to it.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

BlackFin does that. It has 2xinputs and 2xoutputs and one clock signal per each of the two DSP serial ports.

Another good CPU for this application could be the MPC55xx from FreeScale. I haven't used it myself yet, however it looks very impressive.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

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