PLL and SYNC question

What do you mean by error-linearity?!?

Huh? 4046's only work into the low MHz; with big enough capacitors they'll work down to the single-digit Hz.

This is just something you'll have to live with.

I've implemented software PLLs up to 80kHz on modern DSP chips. You need to have a fast DSP to be able to update the control loop at that rate, or you need to figure out how to subsample the input without messing up. If you can generate a sine wave at 20kHz in your DSP you must be turning a routine over at over 40kHz, so I assume you have a fast DSP.

The key is to use a timer for the phase detector. If you have a timer capture input you can capture the timer's phase at the instant that the input signal happens. If you use the same clock that's generating your sine wave for input capture you can easily relate the input phase to your output phase.

Yes, your loop will be more complex. But with this complexity you can buy easy linearization, gain scheduling to account for the changing sampling rate as your input rate gets low, and good fast rough frequency estimation to start your NCO at the right frequency and phase for quick locking.

--
Tim Wescott
Wescott Design Services
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Tim Wescott
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Hello,

I'm dealing with synchronisation issue, that is a big problem for me. I read some ebooks about PLL so I understand (theoretically) its functionality.

My DSP must be able to generate (internally) a sine wave which is frequency-locked to an external TTL reference signal with an error about 0.01Hz (at 20kHz). The frequency range of the external signal is

20Hz-20kHz. I use the DSP in place of VCO, but it doesn't work proper.

More detailed: ext. TTL signal -> PLL SIGin -> PFD -> Loop Filter -> ADC -> DSP ->

DAC -> Comparator -> PLL COMPin.

My problems are 1. External signal is variable (and I can't get some error-linearity after loop filter for the whole freq-range). 2. All commercial PLLs (such xx4046 and xx9046) are designed for MHz-range, and not for my little 20kHz.

Settling time is depending on the sampling frequency (not so good too?).

I read about software PLL and I think that it's too complex to implement for frequencies up to 20 kHz. ADPLLs...hmmm, I can't imagine, how I use it form my design (I mean available xx297 PLLs), but I'd rather do all digitally.

Can you help me with an advice how I do this synchronisation? Maybe there are another ways to do it.

Thank you in advance kirgizz

Reply to
kirgizz

"Frequency error" is a useless spec. When a PLL is locked, there is no frequency error. But there is phase noise, spurs, etc.

Not true, 4046's work great at that frequency range and much lower too.

I suspect your main problem is specifying what you want. If you tell us what comes in and what goes out, there's probably an easy solution.

If it really is a 20kHz signal in (TTL? Square wave?) and you want a

20kHz sine wave out there are much easier solutions than a software DSP PLL.

Tim.

Reply to
Tim Shoppa

Have a look at an Analog Devices DDS chip - they started off with the AD9850 but they now have a page of so of them on their web-site covering a wide range of prices and speeds.

That could be your software controlled oscillator, and would do 20kHz very nicely - the frequency resolution is about 0.001Hz and you can do phase increments and decrements as well as very fine frequency adjustments, which should get all the busy stuff out of your DSP . If you wnat to get fancy and set up in-phase and quadrature phase detectors, Analog do a couple of DDS chips that synthesise both in-phase and quadrautre outputs.

--------------------- Bill Sloman, Nijmegen

Reply to
bill.sloman

to Tim Wescott

Thank you for the quick answer.

I didn't mean the phase comparator output but transient phase error signal after the loop filter (that must be fed to the VCOin). I implemented 1st order passive low pass filter as the loop filter. You know in this case you have not the same signal forms if you have

100 Hz or 20kHz loop input.

I agree. But I don't use VCO.

Really? Great performance (I'd like to have too). My DSP is SHARC ADSP21262 running at 200 MHz. I think it's suitable. But there are another algorithms to be implemented in my design (filters).

I used to capture period of the TTL-input by the timer and to generate corresponding sine wave. This worked very well for 100-Hz but was not precise for 20KHz input. Did you use 1 timer for the phase detector? Could you describe the whole process more detailed, please?

frequency

Yes, I'd like to implement a software PLL and escape using additional hardware. Did your implemented SPLL worked for defined frequency only or for a frequency range, how large was the lock range? My software must be able to lock to frequencies from 20Hz to 20kHz.

Regards kirgizz

Reply to
kirgizz

to Tim Shoppa

Thank you.

I agree.

In order to implement an lock-in amp on DSP I want to generate 2 quadrature sine waves internally. And they must be locked to an external reference signal.

TTL reference goes in, frequency range is 20Hz-20kHz. Reference is variable and ref.frequency sweep is possible.

Regards kirgizz

Reply to
kirgizz

Thank you Bill

Yes, I accept this DDS chips as an option. However, I'd rather do it without any additional hardware. Of course, I can preciselly set the phase/frequency by DDS. In my design DDS-output must be locked to the external reference frequency so I need some sort of lock-detection and phase comparator too. The main problem of synchronisation is not solved. (Or am I wrong?)

Regards kirgizz

Reply to
kirgizz

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