I'm doing the placement on this one. I have the circuit in my head, and I know about the many electrical constraints, so it's easier to do the critical stuff myself, instead of trying to explain it all to my layout people.
The issue now is, can this be done in 6 layers? Probably not, but only the FPGA-DDR3 bit really needs 8. The FPGA needs 5 pours: gnd, +3.3,
+1.8. +1.5, +1. That will eat layers.The big empty areas will be filled in later, after I figure some more things out. My guy can try routing the dense part now.
Placement is weird. You push and rotate things around in pretty much horrible chaos for a long while, then something crystallizes and it all starts to work. It might have randomly settled into some other, likely better, pattern if it was played with longer, or just started at another time or another sequence. That's profound somehow.