placing a board

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I'm doing the placement on this one. I have the circuit in my head, and I know about the many electrical constraints, so it's easier to do the critical stuff myself, instead of trying to explain it all to my layout people.

The issue now is, can this be done in 6 layers? Probably not, but only the FPGA-DDR3 bit really needs 8. The FPGA needs 5 pours: gnd, +3.3,

+1.8. +1.5, +1. That will eat layers.

The big empty areas will be filled in later, after I figure some more things out. My guy can try routing the dense part now.

Placement is weird. You push and rotate things around in pretty much horrible chaos for a long while, then something crystallizes and it all starts to work. It might have randomly settled into some other, likely better, pattern if it was played with longer, or just started at another time or another sequence. That's profound somehow.

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John Larkin         Highland Technology, Inc 

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jlarkin
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Board looks like it has a lot of wasted space and could be at least an inch or so shorter. I see possible layout problems regarding that BGA?/UB2 in the middle, and so maybe more vertical space. Those 3 low voltages could be derived right at the pins where needed; see no reason to have an extra layer just for them. Might save 3 layers on that.

Just thoughts from a dumb growling baer.

Reply to
Robert Baer

It goes behind the front panel of a 19" rack box, and among other things spreads out the front-panel connectors and LEDs where they need to go. The ribbon cable connectors have specific targets too.

I have plans for the empty spaces. I packed the parts to leave some spaces open.

That's a DDR3 DRAM chip above the FPGA. The traces need to be short. We'll try to route that first and see how it goes. I needs 5 mil traces to squeeze between the balls.

We'll go for 8 layers.

The problem with the FPGA is that the various power voltages (3.3,

1.8, 1.5, 1.0) are on an inter-tangled mess of balls. So power pours will fight one another to get at them, and to get at the bypass caps outside of the BGA footprint. The easy fix is to use more layers.
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John Larkin         Highland Technology, Inc 
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John Larkin

Simulated annealing is one way to go for such problems if you can describe a function of merit for the rats nest mesh of lines. It may still need a bit of human guidance to get started but it can do the grunt work and jump to possibilities a human might never consider.

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Regards, 
Martin Brown
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Martin Brown

I don't like autorouting software, because it tends to do really dumb ugly things. And routing is one of the (relatively) fun parts of layout.

The Brat loves to lay out boards, especially BGAs. She turns off the rubberbands, which totally weirds me out, but her boards are beautiful.

Has anyone tried autoplace software? That is a mind-boggling thing.

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John Larkin         Highland Technology, Inc 
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John Larkin

Looks like an unfortunate amount of crossings in your rats nest between the FPGA and RAM (that wouldn't be fixed by rotating). If you could mount the DDR3 on the back, it might save you a couple layers in routing.

Reply to
DemonicTubes

My layout guy is trying to route that now.

The Artix7 FPGA doesn't have a hard DDR3 DRAM controller, but the tools can build one using the usual resources. Unfortunately, it picks the pins when it does that. Data lines can be arbirtarily swapped, within byte groups, but commands to the DRAM are sent over the address lines so they can't be swapped.

If it's horrible to route, we could consider some swapping.

The DDR has a minimum clock frequency, 300 MHz I think, so the address and data lines can't be arbitrarily long. For this case of a single DRAM chip, only one signal from the FPGA to the ram is explicitely terminated, the clock diff pair. That sure helps.

It would be nice to have a small platform board that encapsulated the compute/FPGA core across multiple projects. We have used MicroZed a few times, but it wasn't a good fit here.

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John Larkin         Highland Technology, Inc 
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John Larkin

torsdag den 21. november 2019 kl. 00.37.03 UTC+1 skrev John Larkin:

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too big, or the connectors too pedestrian?

Reply to
Lasse Langwadt Christensen

It will pick the pins only if you don't do it. You can pick the pins yourself (e.g. to get a better address group order), enter them into the tool and have it say whether it likes them or not. The MIG user manual explains the banking restrictions. You should also go through an entire FPGA build, if you want to be absolutely sure it can route to speed.

Allan

Reply to
Allan Herriman

I found those the other day - have you used them ?

If John fancied something a bit more mainstream these look nice:

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MK

Reply to
Michael Kellett

I don't drive the Xilinx tools myself, and my FPGA guys are fairly busy, and are really down on the Xilinx tools lately, so I don't want to launch a big project, which would involve a lot of interaction between the layout people and the FPGA people and me.

I think just some data line swapping will make this routable. The DRAM is for some future options, and the board will likely go to rev B eventually, so we can probably test the DRAM on rev A and tweak if needed. I should fine-tune the routing myself, after my layout guy does it.

The last Xilinx-DDR3 thing that we did worked first pass.

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But we are running at the slowest legal speed for the ram, 300 MHz. Those traces are maybe an inch long.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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jlarkin

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