Phase Noise vs. Jitter

Caveat: something I've found with some of those SS regulators is that they use an internal spreading clock that causes spurs at frequencies that the FCC doesn't care about but that I do. Worth keeping in mind if you are using a spread-spectrum regulator for purposes other than passing CISPR...

-- john, KE5FX

I have a box running on my bench that uses the TPS54302. I'll check the spectrum tomorrow.

John Larkin posts an insulting misapprehension of my technical contribution to the thread, and then complains that I'm only here to insult.

And Larkin's is sadder than most.

Oh, that's boring. Must be a case of unanswered love.

G.

It's certainly about rejection. Sloman wanted me to hire him, and I didn't.

It's difficult to get more dumbed down than the usual engineering approach with their damn graphs of "fuzzy" phasors and pulling equations out of the air full of undefined terms. See eq. 106 of section 2.110.3A etc idiocy.

I snooped the switcher node, Rigol scope FFT and a big ole spectrum analyzer, but neither is dramatically instructive.

John Larkin complained that he couldn't hire skilled help, and I pointed out that I was retired and willing to sub-contract by e-mail (which I've done, but not much).

He passed the email on to Jim Thompson, who persuaded him that it would not be a good idea, and posted a rude comment - gloating about his success - here.

This didn't endear John Larkin to me. He was welcome to reject my offer, but passing it on to Jim Thompson was decidedly bad behaviour on his part.

And he recklessly repeats defamation from sources he doesn't even know. The n he lies about having communication with that source, when it's obvious th at he has. He's doesn't realize he's been communicating with a pedophile, c areer malingerer and ne'er do well.

On Wednesday, September 18, 2019 at 7:27:11 PM UTC-7,

Hmm, and now I can't repro it here, either. At one point I was getting a lot of EMI at 30 kHz (IIRC) from this setup in spread-spectrum mode:

Of course I didn't save any plots at the time, or keep any actual notes. Oh, well, guess it fixed itself.

-- john, KE5FX

My FPGA kids refuse to use enough core current to get my switcher out of burp mode. They should compute pi to a trillion places or something. Burp complicates the spectrum.

Here's the board.

Seems to work first try. My big mistake was making the blue LED too bright, but I think we'll fix that in the FPGA.

Am 20.09.19 um 19:44 schrieb John Larkin:

Tell them to make a LFSR counter with 10K flipflops and toggle it with the highest clock they have on the chip. Binary counters do not work. There, the lowest bit takes all the power, the higher bits don't "count".

I feel somewhat guilty.

Gerhard

Won't that make the test results rather random? (grins, ducks, leaves room quickly)

Period = 2^10000 - 1

One problem is to keep the compiler from optimizing out something that has no function. The fix is to do something that is too complex for the compiler to understand, and bring it out to a pin.

Am 20.09.19 um 22:20 schrieb John Larkin:

The run length does not matter. The point is that about half the FFs toggle each clock. Having one output pin to nirvana is the easiest way to make sure that it is not optimized away.

I once had a huge FIR-Filter after a 2's complement ADC. I switched it ON for the first time and was pleased by the low power consumption. After some seconds, consumption exploded. I switched it all off, assuming that there was sth. burning off.

But no, it was just the analog ADC bias control loop doing its duty, so the minimum noise produced alternating 00000001 and 11111111 and that was about the worst, energy-wise, for the adders and multipliers.

Working against the Xilinx optimizer can be hard. I did a VHDL package for a triple module redundancy replacement for std_logic, std_logic_vector, signed etc, where the redundancy was hidden mostly in the package. I ended up with extra input pins my_high, my_low, my_perhaps for all of the 3 components. Clutters routing somewhat, but it is fun to see a counter simply counting on, in spite of a dozen of bit errors injected each cycle. Somehow like the Terminator coming unimpressed out of the flames of a burning gas truck. Just do not hit more than 1 FlipFlop of the same bit at the same time.

No, we did not get the Xilinx redundancy tool because of ITAR, for sth. that will go to ISS. :-[ But my solution is now better anyway. :-)

Gerhard

Oh... so _you_ must be the guy who was responsible for that dreadful shortage of 74LS12AX7 "quad maybe-gate" chips a few years ago?

If so, please know that you _totally_ messed up the parts-acquisition schedule for a project I was working on (the embedded controller for an updated Infinite Improbability Drive system). :-)

John Larkin wrote in news: snipped-for-privacy@4ax.com:

That could just be an effect of the camera angle and that specific LED's reflecto-dish. Or like you said... a different current limit resistor driving it.

snipped-for-privacy@coop.radagast.org (Dave Platt) wrote in news: snipped-for-privacy@coop.radagast.org:

You guys have just stumbled onto the world's only truly random number generator!

snipped-for-privacy@coop.radagast.org (Dave Platt) wrote in news:h6uf5g-ciq.ln1 @coop.radagast.org:

Firesign Theatre

Don't Crush That Dwarf, Hand Me The Pliers