Phase Noise vs. Jitter

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Gentlemen,

I thought these terms were effectively the same thing, but now I'm not so  
sure.  
Taking a square waveform of uniform amplitude for the sake of simplicity,  
AFAIAA, if I'm looking at such a wave in the time domain with an  
oscilloscope and I'm seeing intermittent thickening of the vertical  
portions of the trace, that's jitter. But if the frequency of the wave is  
more slowly varying, then that's phase noise, which can be observed with  
a spectrum analyser (frequency domain) as the presence of unwanted  
sidebands on what would be an otherwise infinitely thin vertical peak if  
the wave had perfect spectral purity. Do I have that right?  
<cue massive argument, probably>

TIA



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Re: Phase Noise vs. Jitter
On Sun, 15 Sep 2019 00:25:46 -0000 (UTC), Cursitor Doom

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There's a math operation that maps one into the other, at least for
wideband noise and RMS jitter. There are several calculators online.

One of the guys here did this:

https://www.dropbox.com/s/zkhw9nlkwurcy7q/PhaseNoise102.exe?dl=0

In the telecom business, stuff below 0.1 Hz is called "wander" and
faster wiggles are "jitter."





Re: Phase Noise vs. Jitter
On Sat, 14 Sep 2019 20:06:46 -0700, jlarkin wrote:

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I don't want a mathematical explanation, though; just an intuitive one.  

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In that case I've discovered a new phenomenon I've dubbed "twitch". :-)

"Exe files can't be previewed" it says on your link.

Let's try re-phrasing it thus: phase noise produces sidebands. Does  
jitter?



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Re: Phase Noise vs. Jitter
On Sunday, September 15, 2019 at 7:14:27 PM UTC+10, Cursitor Doom wrote:
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Something dumbed down enough for Cursitor Doom to understand.
  
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The kind of deviations from the ideal perfectly repetitive waveform that constitute phase noise, and can be characterised as jitter, show up as low level sidebands on the Fourier transform of a noisy and jittery waveform.

--  
Bill Sloman, Sydney

Re: Phase Noise vs. Jitter

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  clock jitter.

<https://about.keysight.com/en/newsroom/imagelibrary/2006/02may-
em06067/>

<https://about.keysight.com/en/newsroom/imagelibrary/2006/02may-
em06067/image001.jpg>

Re: Phase Noise vs. Jitter
On Sunday, September 15, 2019 at 7:04:48 AM UTC-4, Bill Sloman wrote:
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It's difficult to get more dumbed down than the usual engineering approach with their damn graphs of "fuzzy" phasors and pulling equations out of the air full of undefined terms. See eq. 106 of section 2.110.3A etc idiocy.

Re: Phase Noise vs. Jitter
On Sun, 15 Sep 2019 09:14:23 -0000 (UTC), Cursitor Doom

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Download it and run it. It's cool and perfectly safe.

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Sure. If the period of a signal isn't exactly constant, then it's
frequency is being modulated. And FM makes spectral components in
addition to the main frequency spike.

If the jitter is fast and random, the frequency-domain noise floor is
wideband, so a spectrum analyzer might not show classic sidebands,
just an elevated noise floor. But some kind of systematic jitter, like
time wobble caused by power supply ripple, will make classic looking
sidebands around the main frequency line; FM.

I often measure jitter as a function of time. The shortest time is a
single cycle of a waveform, which is what you usually see on a scope.
But you can measure one rising edge relative to the 10th edge away, or
the millionth one. A graph of jitter vs time correlates directly with
the phase noise graph of the oscillator. Low frequency phase noise
makes long-timebase jitter. You can, in theory, measure the jitter of
a 1-year time delay; it will be huge.

A cheap crystal oscillator will have maybe 10 nanoseconds of RMS
jitter when it's used to time out one second of delay. A really good
OCXO will have a few picoseconds. The phase noise plots are indicators
of the jitter behavior.

Allan variance is one formal way of expressing the complex phase
noise/jitter of an oscillator.


Re: Phase Noise vs. Jitter
On Sun, 15 Sep 2019 08:17:08 -0700, jlarkin wrote:

[...]

Thanks, John. That's exactly the clear explanation I was looking for. Now  
watch some awkward bastard come along and find fault with it. :-)



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Re: Phase Noise vs. Jitter
On Sun, 15 Sep 2019 15:29:03 -0000 (UTC), Cursitor Doom

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One fun thing is spread-spectrum switching regulators. They jitter
hard in time domain, to spread out the RF spectrum and pass FCC
limits. It is sort of cheating.

https://www.dropbox.com/s/s9aqx1z3glab423/TPS54302_PWM.JPG?raw=1

It surprised me that the DC output is very quiet. They must shape the
timing of the jitter, like a 2nd order delta-sigma modulator, to push
the noise spectrum up where the output filter kills it.



Re: Phase Noise vs. Jitter
On Monday, September 16, 2019 at 11:20:49 AM UTC-7, John Larkin wrote:
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Caveat: something I've found with some of those SS regulators is that  
they use an internal spreading clock that causes spurs at frequencies  
that the FCC doesn't care about but that I do.  Worth keeping in mind  
if you are using a spread-spectrum regulator for purposes other than  
passing CISPR...

-- john, KE5FX

Re: Phase Noise vs. Jitter
On Tue, 17 Sep 2019 20:10:28 -0700 (PDT), "John Miles, KE5FX"

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I have a box running on my bench that uses the TPS54302. I'll check
the spectrum tomorrow.


Re: Phase Noise vs. Jitter
On Tue, 17 Sep 2019 21:27:10 -0700, snipped-for-privacy@highlandsniptechnology.com
wrote:

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I snooped the switcher node, Rigol scope FFT and a big ole spectrum
analyzer, but neither is dramatically instructive.

https://www.dropbox.com/s/67zt446nx37o0c9/TPS54302_PWM.JPG?raw=1

https://www.dropbox.com/s/20rofrdeh22sc6r/TPS54302_FFT.JPG?raw=1

https://www.dropbox.com/s/zr1ouuipkfa3v95/TPS54302_spectrum.JPG?raw=1




Re: Phase Noise vs. Jitter
On Wednesday, September 18, 2019 at 7:27:11 PM UTC-7,  
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Hmm, and now I can't repro it here, either.  At one point I was getting  
a lot of EMI at 30 kHz (IIRC) from this setup in spread-spectrum mode:

http://www.ke5fx.com/LT8650S.gif

Of course I didn't save any plots at the time, or keep any actual notes.  
Oh, well, guess it fixed itself.

-- john, KE5FX

Re: Phase Noise vs. Jitter
On Fri, 20 Sep 2019 03:05:50 -0700 (PDT), "John Miles, KE5FX"

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My FPGA kids refuse to use enough core current to get my switcher out
of burp mode. They should compute pi to a trillion places or
something. Burp complicates the spectrum.

Here's the board.

https://www.dropbox.com/s/45i9bfmzr9b2pf5/TPlus_E2_Leds.JPG?raw=1

Seems to work first try. My big mistake was making the blue LED too
bright, but I think we'll fix that in the FPGA.


Re: Phase Noise vs. Jitter
Am 20.09.19 um 19:44 schrieb John Larkin:

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Tell them to make a LFSR counter with 10K flipflops and toggle it with
the highest clock they have on the chip. Binary counters do not work.
There, the lowest bit takes all the power, the higher bits don't "count".

I feel somewhat guilty.

Gerhard


Re: Phase Noise vs. Jitter

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Won't that make the test results rather random?  (grins, ducks, leaves
room quickly)





Re: Phase Noise vs. Jitter
snipped-for-privacy@coop.radagast.org (Dave Platt) wrote in

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  You guys have just stumbled onto the world's only truly random  
number generator!

Re: Phase Noise vs. Jitter
wrote:

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Period = 2^10000 - 1

One problem is to keep the compiler from optimizing out something that
has no function. The fix is to do something that is too complex for
the compiler to understand, and bring it out to a pin.


Re: Phase Noise vs. Jitter
Am 20.09.19 um 22:20 schrieb John Larkin:
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The run length does not matter. The point is that about half the FFs  
toggle each clock. Having one output pin to nirvana is the easiest way
to make sure that it is not optimized away.


I once had a huge FIR-Filter after a 2's complement ADC. I switched it
ON for the first time and was pleased by the low power consumption.
After some seconds, consumption exploded. I switched it all off,
assuming that there was sth. burning off.

But no, it was just the analog ADC bias control loop doing its duty,
so the minimum noise produced alternating 00000001 and 11111111
and that was about the worst, energy-wise, for the adders and
multipliers.


Working against the Xilinx optimizer can be hard. I did a VHDL package
for a triple module redundancy replacement for std_logic,  
std_logic_vector, signed etc, where the redundancy was hidden mostly
in the package. I ended up with extra input pins my_high, my_low,
my_perhaps for all of the 3 components. Clutters routing somewhat, but
it is fun to see a counter simply counting on, in spite of a dozen of
bit errors injected each cycle. Somehow like the Terminator coming
unimpressed out of the flames of a burning gas truck.
Just do not hit more than 1 FlipFlop of the same bit at the same time.

No, we did not get the Xilinx redundancy tool because of ITAR, for sth.
that will go to ISS. :-[
But my solution is now better anyway.  :-)

Gerhard


Re: Phase Noise vs. Jitter
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Oh... so _you_ must be the guy who was responsible for that dreadful
shortage of 74LS12AX7 "quad maybe-gate" chips a few years ago?

If so, please know that you _totally_ messed up the parts-acquisition
schedule for a project I was working on (the embedded controller for
an updated Infinite Improbability Drive system).  :-)





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