PCB trace spacing with soldermask

According to my old Bishop Graphics catalog, coated traces at 100V, spacing should be 0.020" minimum. This chart is based off MIL-STD-275D. 5 mils for 100V doesn't sound right.

I'm seeing a lot of conflicting advice. Somewhere I recall seeing .2mm (.008") spacing being good for up to 100VDC. At the link below, the Gecko drive fellow (Mariss Freimanis) indicates that .0125" is fine for 100VDC;

Are you sure that wasn't 0.5mm?

first hit on google:

-LAsse

Been there d>

This table is close to the one in OP;

but are they trustworthy? Values too low?

If that were the case you'd never get a trace between BGA pads, making them rather useless.

More confusion;

"It is interesting to note that many major power supply manufacturers in their low-power designs are widely using 500-600V MOSFETs in TO220 package operating at 400V and higher. With this package you can have about 30 mils spacing between the pads while IPC would require at least 100 mils. Even if you spread the leads on the PCB, you can't do anything with 50-mil spacing between the TO220 leads along the surface of the package."

The above underscores the "inexact science" at work here. Rather than follow some table or rule, it probably makes more sense to follow what some tried and true product has been able to get away with. I'm inclined to believe what is said in the link below since that G320 product has been around for about ten years.

em

Why would you run 100V DC between BGA pads?

"Up to 100VDC" means anywhere from 0 to 100VDC. Just like sale prices of "up to 50% off". An idiomatic expression.

Best regards, Spehro Pefhany

I guess that depends on how you interpret "for voltages up to 100VDC". 3V is certainly below 100V.

V is

And if 3V is all the device needs to handle then a commensurate device package would be used. The device package the manufacturer chooses usually takes into consideration the device voltage rating. Even if a relatively fine pitch package is associated with a relatively high voltage (100V transistor arrays for example), it's hardly likely that you'll find collector and emitter terminals adjacent for example.

There is only one sensible way to interpret "for voltages up to

te:

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them

Occasionally you need to:

e.g

I designed a product where we had over 3000 nets with up to 200V on each line that terminated in 1mm pitch 400 pin array connectors.

We found that even with 4mil spacing breakdown didn't occur until about 2KV for surface traces and about KV for buried traces on ordinary FR4.

It was tricky getting UL approval because they wanted huge spacings. These nets were not a safety issue so we did get it eventually.

kevin

Try reading, this time with your brain turned on.

Wrong. This phrase can also be read as "these groundrules apply for all voltages up to 100V".

Are you referring to some internally generated 100 VDC from a high impedance source or perhaps some external signal conductors (such as the telephone circuitry) or even some rectified mains ?

When dealing with tracks that are connected to some external wiring (such as mains or telephone) one should expect much larger peak voltages than the nominal voltage.

In Europe on the ordinary 230/400 Vac mains feed, the system is expected to tolerate 1.5 kV peak voltages, thus the PCB track separation must be considerable.

Assume a voltage of 100VDC or 100V peak.

Kev>

You're try>

Cheers

Phil Hobbs