OT: Integrator Windup and Spice Modeling

Good lord -- no answers?

I'm assuming you want some behavioral measure, not whatever is "real" (i.e., the max achievable voltage on a cap vs. the max voltage that it has effect, ditto for min). If so, then the recovery time may be useful -- but even that would probably need to be further quantified.

I could see it turning into a big snarly can-o-worms -- how often you you actually have to care in real circuit design?

I couldn't care less >:-} I'm making Spice models and musing what the masses want to input as data points to make the model work as they expect. ...Jim Thompson

Well, it's cool that you're doing it.

When does integrator windup cause problems with op-amp circuits? Is it just when the thing's been on the rail, or are there other times, too?

I was going to stick my nose in the air and say I always use comparators in such situations, but there are times when I'll use a R-R op-amp and depend on it hitting the rail and coming off the rail in some degraded yet still good-enough way.

Output hits rail, input diff stage continues to drive comp cap (at diff-to-single-ended-node, DTSEN) until that nodes rails as well... which results in a recovery time until DTSEN gets back to proper Q-point.

For clients that provide me with a device-level netlist, there's no issue, I just match behavioral to device-level. From datasheet I hope for a definitive statement for conditions of recovery time.

The real world is paved with control loop screw-ups ;-) ...Jim Thompson