I got a design example from my old Ludwig-Bretchenko textbook to simulate on Ngspice 29. It uses a BFQ65 RF BJT(NXP Semiconductor) in a common base configuration. The design frequency is 1.5 GHz. The collector and emitter are terminated with impedancesthat match the transistor impedances at those terminals. These impedances are all calculated from the S parameters., and transistor biasing is as per the provided specifications. A damped high amplitude sine wave trigger signal at one of the emitter at the same frequency(1.5 GHz) kick starts the oscillations.
Fourier transform of the output puts the fundamental at 1.41 GHz. I will of course improve this. A damped
The transistor was biased in the standard way for Vc = 0.5Vcc and Ve =
0.1Vcc. It also
ely the S, Z matrix etc., come
The netlist is below. Beta(min) for the BFQ65 is 60, and Ic(max)=50 mA, s o Ic value selected for this design is 35 mA. Vcc is 12V. A separate C prog ram calculates all the biasing resistor values, PI network capacitor, input , output capacitor values, SPICE transient analysis sampling time etc.,
I would strongly suggest that you look at a differential oscillator. These are de-facto *the* standard topology in asic design. Its gain is much better than a single transistor Colpitts etc, of which, essentially, no one uses in those aforementioned billions and billions of products. Pretty much only xtal oscillators use single ended oscillators in asic products.
The concept is shown here:
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Unfortunately, and very sadly, the only other asic poster that regular posted to this NG (Jim Thompson), is no longer with us it would seem. The point here is that, techniques that are actually the norm, i.e most used by sheer numbers, are not typically used for board level design, which is most of the experience, I believe, in this NG.
JT posted a differential oscillator in LTSpice format several years back when I was simulating a lot of oscillators. It was quite informative, but it worked *really badly* compared to what I already had. He also posted one with AGC, again an interesting topology, except the AGC was biassed wrong and was doing nothing; the amplitude was actually controlled by limiting. I managed to fix his AGC circuit, but I never built the diff osc.
It is very easy to take a good topology, and make it work badly...
I would repeat that the differential topology is pretty much a/the standard for non-xtal oscillators in asic products. The higher gain is a strong decider.
AGC is usually much more agro than its worth. A basic issue, is that just adds more noise.
Yes. Very, very common for circuits to be working not in the manner that they are believed to be working.
I might have a go at creating an example for my yearly SS update...
I wonder how much and in what way does the ASIC technology limit the oscillator performance. Discretes may have some other problems or limits. And low voltage is common to both. How to get the best is IMO more interesting than the technology.
on the plus side, there is essentially, no inductance... on the negative side, there are essentially, no inductors....
I would have thought the advantages of ASICs for high frequency were pretty apparent. No transmission line parasitics, no cap parasitics, no inductor parasitcs, digital tuning. As far as the "oscillator" goes an ASIC oscillator may well have several internal ldos, chebychev temperature compensation, varactor linearization, clipped sine and cmos output buffers etc... etc... Its a no brainer. Typically an oscillator asic will have like
5,000 to 10,000 analog transistors doing all sorts of shit, all in a couple of mm square, at 20 cents...
m. The transistor was biased in the standard way for Vc = 0.5Vcc and Ve = 0.1Vcc. It also
iately the S, Z matrix etc., come
A, so Ic value selected for this design is 35 mA. Vcc is 12V. A separate C program calculates all the biasing resistor values, PI network capacitor, i nput, output capacitor values, SPICE transient analysis sampling time etc.,
?
Please take a look at the .PARAMS directive at the top of the netlist. All values are listed there. I have tried larger time durations fort the .TRAN analysis, but that does niot make any difference.
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