op-amp common mode input resistance

Hello, in

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R is in parallel with the + input of the op-amp which presumably will have = a resistance to the power terminals and hence ground for AC signals. For a= 741 op-amp this seems to be in the MOhm range. Would you expect this to a= lter the time constant significantly? e.g. if R was around 100K any resist= ance in parallel would have to be at least 100Meg to keep the time constant= to within 0.1% of un-loaded value.

I ask because I built one using a MC1458 and it does not seem to be affecte= d by loading as described and I would expect it to be (I actually thought I= would need to use a JFET or CMOS op-amp)

Thanks

Reply to
davew
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That is not the kind of circuit that has 0.1% accuracy. Your cap will be

1% at best.

As a rule, I always use filter circuits based on integrators (plus input at ground). This takes more op amps, often more than one per pole, but the results are more repeatable. I'll try to find the generic circuit later. I have some schematics, but can't post them.

Reply to
miso

=20

=20

True and I have used 1% caps with 0.1% resistors, but if you take a 100K //= 2Meg (assumed input resistance to gnd), the error is 5% hence my question.= 1% tolerance is fine, 5% isn't really.

So what I really need to know is what is the resistance for bipolar inputs,= and does it really matter (my measurements suggest not)- most datasheets p= rovide a single value Ri or ri and I think this is the differential mode in= put resistance which doesn't really matter so much since both inputs are at= approximately the same potential anyway.

Thanks.

Reply to
davew

e a resistance to the power terminals and hence ground for AC signals. For= a 741 op-amp this seems to be in the MOhm range. Would you expect this to= alter the time constant significantly? e.g. if R was around 100K any resi= stance in parallel would have to be at least 100Meg to keep the time consta= nt to within 0.1% of un-loaded value.

ted by loading as described and I would expect it to be (I actually thought= I would need to use a JFET or CMOS op-amp)

The TI datasheet lists it as 200 Megaohm

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Reply to
bloggs.fredbloggs.fred

Op-amps are generally constructed such that the input pins are nearly isolated from the power pins, and mostly "talk" to one another. The effective resistance between the pins is multiplied by the op-amp gain, which is going to be very large unless you're operating at close to its GBW product.

And -- don't think that just because a FET has low resistance at DC it has low resistance at AC. The effects are there, they just end up acting through the gate capacitance.

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com
Reply to
Tim Wescott

ave a resistance to the power terminals and hence ground for AC signals. F= or a 741 op-amp this seems to be in the MOhm range. Would you expect this = to alter the time constant significantly? e.g. if R was around 100K any re= sistance in parallel would have to be at least 100Meg to keep the time cons= tant to within 0.1% of un-loaded value.

ected by loading as described and I would expect it to be (I actually thoug= ht I would need to use a JFET or CMOS op-amp)

Great, thanks for pointing that out. I think my problem is now solved.

Reply to
davew

I really wonder if this is real. The 1458 is basically a 741. So you have say 2M looking into the input. Put that in series with the Ro of the the input pair and I don't believe it would be 200Mohm. This spec isn't tested, just typical. No test circuit diagram, so assume open circuit. The only information is the test is done at 20Hz.

I dug up my copy of Gray/Meyer and they put the input stage transistor Ro at 9Mohm.

Reply to
miso

Looks like the basic 741 architecture has undergone several revisions since= the original Fairchild release. The 200M is believable since there is no i= nternal path from the input biasing to ground and it employs negative feedb= ack through several current sources to balance the common-mode currents in = the input stage. Negative feedback usually implies very high input impedanc= e. Most of the data sheets don't even list it, although most are in agreeme= nt about the 2M differential input resistance.

Reply to
bloggs.fredbloggs.fred

Do you have a schematic? I looked for test data on the internet and couldn't find any.

I don't get this statement: "there is no internal path from the input biasing to ground"

What op amps have paths to ground? There isn't even a ground pin. And if feedback circuits are doing the magic, you can bet on a low power part like a 741 the feedback loop bandwidth is not very high.

As I started earlier, using circuits where the positive inputs are at ground takes common mode issues out of the picture. Further, such designs reduce the number of high impedance nodes, which is always a good thing if you are concerned about unintended signal coupling. The draw back is more power. It looks like I took that design off the PC, but I'm pretty use it was 4 op amps for two poles. Certainly 3.

I designed a lot of SCFs in the day when they were useful, so I know signal flow techniques. Hard to break old habits, especially when they are good ones.

Reply to
miso

At signal frequencies power and gnd are pretty much equal (well at least they should be)

Reply to
davew

should be)

Do you mean the positive and negative rail?

Reply to
miso

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