one-IC digital PLL?

A simple oscillator locked by injection sure is simple. May not get you clean enough spectrum though.

NT

see

When you say, "

Ok, you want a digital clock at 4/9 or 4/7 the frequency of an input clock at less than 20 MHz. That input frequency is a bit low to use the internal PLL of various FPGAs. But it might work if you can double the input clock rate to around 40 MHz. Not sure how low you want the input to go.

There are very small FPGAs these days, some around 5 mm square or less.

A long time ago, I used a TI 74LS297, which will do most of the job. But, I think you will still need an outboard counter with that one. (They now have the HCT297, too.) There might be something newer that includes the counter, too. But, then you might need to program the counters with a CPU.

Jon

the input is between 14 and 18 MHz actually. The suggestion do check IDT product was really good anyway, I would use the ICS525-01 if it would guarantee the phase relationship between the two clocks. The ICS527 does guarantee the phase relationship but has an input gap right where I need it and it doesn't have an internal xtal oscillator (so more external parts....) I keep looking

yes, but if I can avoid the software part, I will :-)

Thanks Frank IZ8DWF

yep a '297 based solution requires at least some other external parts (VCO too probably). I'll see how much space it requires though, maybe it can be ok.

Thanks Frank IZ8DWF

If it's the firmware design I can sort of see your point. If it's the stocking for production, you can just send the design file to your favorite distributor and they'll program the part in-house for you; you can then just treat it like any other chip.

No VCO. It does need a clock that is some multiple of the desired output frequency. Then, it needs a divider equal to the multiplication ratio you want.

Jon

A small FPGA would do it. Divide by 4, divide by 9, phase detector. At most it would need an RC into a VCXO. Probably it could be done without a separate VCXO, using one of the PLLs inside the FPGA.

There are some small cheap "cpld" chips, which are really small FPGAs with internal configuration flash. But not 5 volts; 5 volt logic is getting increasingly rare.

Go really retro with a 74HC4046 and a dual programmable counter?

Is the input clock on any one unit fixed (always from the same crystal) or can it vary from 14MHz to 18MHz during use (e.g. user plugs in external crystal oscillator signal)? If the input clock is fixed on one particular unit is fixed, is the range of 14 to 18MHz just to allow for different models or customer installations?

It seems to me that for widest PLL bandwidth (smallest loop filter capacitors and also least reliance on good VCO performance) it would be best to use the highest comparison frequency possible. Therefore I would multiply the frequency by 4 with a PLL, and then divide down the output of the PLL by a factor of 7 or 9.

You might find that one of the PICs with internal x4 PLL frequency multiplier could be useful, though I don't know whether it is feasible to get it to put out the multiplied clock and/or the multiplied clock divided by 7 or 9.

If you are not averse to inductors then you could also make a tuned frequency multiplier, either a quadrupler or a chain of two doublers. You would have to skew the input duty cycle since a square wave only contains odd harmonics.

It seems to me that by far the best option would be to change your crystal oscillator to run at a frequency 4x higher, and insert a divide-by-four to provide your 14-18MHz clock, and a separate divide-by-seven or divide-by-nine for the other clock. That way you will have excellent jitter on all of the clocks, and no possibility of an un-locked PLL etc. This ought to use less power and be smaller and cheaper too.

Chris

once the xtal is installed, it remains fixed. But it can have different frequencies. The range is broad, but possible frequencies are few (3-4).

yeah, easy if I had the room... I can easily make a 3 chips solution, but it doesn't fit easily.

I'll look into this also... I need to find out if it can divide the x4 clock by 7 or by 9 with good phase lock.

the only constraint in this problem is space, let's say I can use a soic-28 room or slightly more, maybe two soic-28 one on top layer and one on bottom layer, but I think less than that since there's a xtal for sure.

that can't be done, it's a "patch" on another circuit, xtal should really remain the same. Changing it would be the last resort, if all else fails.

yes, but we can't easily tell everyone to pull the existing xtal and solder back a new one (yes, as I said it might be a last resort option).

Many thanks! Frank IZ8DWF

Any PIC with internal fractional PLL in a really tiny package (QFN/DFN)? Exactly one part.

Best regards, Piotr

Or a Cortex-M0.