The image on the below link shows the configuration of NPN transistors bein g used in a dual package.
formatting link
n_zpsg5vgbqwd.jpg
What in the world is going on here?
My analysis:
To me it seems that the capacitor C31 is blocking all DC from the V3.3PWR. Only AC will pass through the capacitors. There then is a resistor divide r R69 and R70 that divides the signal down 10%. The input signal then goes to the base of right transistor. The transistor turns on being pulled to ground with the 100k resistor (R71).
This ?3.3V? of the V3.3VPWR then loops around to the base o f the left transistor. This then turns the left transistor on pulling the RESET_430 line to ground?
. Only AC will pass through the capacitors. There then is a resistor divi der R69 and R70 that divides the signal down 10%. The input signal then go es to the base of right transistor. The transistor turns on being pulled to ground with the 100k resistor (R71).
of the left transistor. This then turns the left transistor on pulling t he RESET_430 line to ground?
On power on the cap is discharged, so the right side transistor turns on tu rning on the left side collector transistor. As the cap charges the base o f right side transistor falls, turning of it and hence the lest side one, t hereby deasserting the reset.
Probably not so much designed as blundered on by random rearrangement of parts.
One problem is the base of the left transistor is subject to an undefined and possibly extremely large peak current. The peak current is limited only by 3.3V less 2*vbe drops and R69 multiplied by the beta of the right transistor. Could easily exceed 50mA.
A simple cure would be to connect C31 straight to the base of the right transistor and insert R69 in series with the base of the left transistor.
. Only AC will pass through the capacitors. There then is a resistor divi der R69 and R70 that divides the signal down 10%. The input signal then go es to the base of right transistor. The transistor turns on being pulled to ground with the 100k resistor (R71).
There is no divider for R69/R70, which is initially 100/110=90% and not 1
0%, but this clamps at 1.3-1.4V across the darlington, at which point it st ops dividing and sinks a constant 1.35/0.1M=13.5uA. Since the input is ca pable of (3.3-1.35)V/10k=200uA, this guarantees the output transistor of Q4 saturates, assuming it's driving a very high impedance CMOS input, which most RESET inputs are. This circuit state prevails until the input current falls to around 13.5uA at which point the Q4 pair turns off abruptly,becau se of the relatively large composite current gain, and terminates the reset .
of the left transistor. This then turns the left transistor on pulling t he RESET_430 line to ground?
POR circuits are nontrivial, if they really work right. I generally use a MAX809 type part (from TI, not Maxim of course) which costs 13 cents and does everything right.
It can be fooled into snooping multiple power supplies, too.
formatting link
--
John Larkin Highland Technology, Inc
lunatic fringe electronics
R. Only AC will pass through the capacitors. There then is a resistor div ider R69 and R70 that divides the signal down 10%. The input signal then g oes to the base of right transistor. The transistor turns on being pulled to ground with the 100k resistor (R71).
e of the left transistor. This then turns the left transistor on pulling the RESET_430 line to ground?
It's not bad. The only suggestion for improvement would be to change R71 to 10K, when the output comes out of the storage time recovery from its extre me base region overdrive, the fall time will then be on the order of 100's ns. If you want to splurge on an extra part, a 100R in the collector of inp ut transistor wouldn't hurt, limits IC to ~20mA where it probably ends up a lready due to beta rolloff of the 847 with IC.
It assumes a practically instantaneous, monotonic power supply rise. It has no brownout detection and no undervoltage sensing. It ignores a short blackout. The first time constant is only 1 millisecond. A lot of timing depends on beta. It can glitch erratically, which could hang up whatever it's resetting. The rise time of \Reset will be slow.
It has a lot of parts, and an average of over one defect per part!
Sounds bad to me.
--
John Larkin Highland Technology, Inc
lunatic fringe electronics
3PWR. Only AC will pass through the capacitors. There then is a resistor divider R69 and R70 that divides the signal down 10%. The input signal the n goes to the base of right transistor. The transistor turns on being pul led to ground with the 100k resistor (R71).
base of the left transistor. This then turns the left transistor on pulli ng the RESET_430 line to ground?
to 10K, when the output comes out of the storage time recovery from its ex treme base region overdrive, the fall time will then be on the order of 100 's ns. If you want to splurge on an extra part, a 100R in the collector of input transistor wouldn't hurt, limits IC to ~20mA where it probably ends u p already due to beta rolloff of the 847 with IC.
You're sounding like a hysterical ninny!
Last time I checked 200uA through 0.1uF is dV/dt on order of 2mV/us. That h ardly sounds like "practically instantaneous...rise" to me. Why don't you t ry doing a calculation once in while...
The power supply caps can hold up through the "short blackout." I see no ti ming that's beta dependent. Rise time of /RST is fast. Who says UVLO is eve n needed.
It's not the best POR in the world- will probably work 99.999% of the time- you could do worse.
Or perhaps wire this as the Darlinton pair they seem to be trying to use. Instead of V3.3, the collector of the right transistor could be connected to RESET_430.
That's actually hard to imagine. These devices are all CMOS with a threshold around Vcc/2. They may spec 0.8 volts, but that is just a holdover from TTL days which is much more common on outputs than inputs. For example the Stellaris LM4F120H5QR Vil is 0.35 * VDD or 1.155 volt when VDD is 3.3 volts.
A typical soft-start switcher, or a PC power supply, will rise slower than that. The first two junction drops are lost, so the slower part of the power supply rise has to do the work. It's terrible.
If you don't want to hang up logic, brownout reset is mandatory. Brownout at the power supply *output*
99.999 is grossly optimistic. *I* couldn't do worse.
--
John Larkin Highland Technology, Inc
picosecond timing precision measurement
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
V3.3PWR. Only AC will pass through the capacitors. There then is a resist or divider R69 and R70 that divides the signal down 10%. The input signal then goes to the base of right transistor. The transistor turns on being pulled to ground with the 100k resistor (R71).
he base of the left transistor. This then turns the left transistor on pu lling the RESET_430 line to ground?
R71 to 10K, when the output comes out of the storage time recovery from its extreme base region overdrive, the fall time will then be on the order of
100's ns. If you want to splurge on an extra part, a 100R in the collector of input transistor wouldn't hurt, limits IC to ~20mA where it probably end s up already due to beta rolloff of the 847 with IC.
t hardly sounds like "practically instantaneous...rise" to me. Why don't yo u try doing a calculation once in while...
timing that's beta dependent. Rise time of /RST is fast. Who says UVLO is even needed.
me- you could do worse.
"The BOR circuit detects low supply voltages and resets the device by trigg ering a power-on reset (POR) signal when power is applied or removed. The M SP430 MCU?s zero-power BOR circuit is continuously turned on, inclu ding in all low-power modes."
"The PMM generates a supply voltage for the core logic, and provides severa l mechanisms for the supervision and monitoring of both the voltage applied to the device and the voltage generated for the core. It is integrated wit h a low-dropout voltage regulator (LDO), brown-out reset (BOR), and a suppl y voltage supervisor and monitor."
"The SVS is a configurable module used to monitor the AVCC supply voltage o r an external voltage. The SVS can be configured to set a flag or generate a power-on reset (POR) when the supply voltage or external voltage drops be low a user-selected threshold."
formatting link
Apparently the MSP430 doesn't need an external POR, it already has one. The OP circuit is intended to drive the /RST/NMI input. Looks like the differe nce between the two resets has to do with IO pin configuration and flag fla gs.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.