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Not attaining required slew rate on differential ADC input buffer

Hello--

I've designed and built a system with a number of AD7690 SAR ADCs. These particular ADCs have differential inputs. As recommended by the manufacturer's datasheet and various application notes, I've selected the ADA4941-1 single-ended to differential driver. This driver has a given slew rate of 26 Volts/microseconds, and is designed to convert a single-ended analog input into two phase-shifted outputs.

I've essentially built this particular circuit:

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I've modified the circuit for a Vin which swings between 0V and +5V. This was easy to do based on the design equations given in the application note. I've also added 0.1uF and 10uF decoupling caps to the positive and negative voltage rails of the ADA4941-1. An inductor is also used on these rails to form an LC filter along with the decoupling capacitors. The inductors are situated close to the voltage inputs. I've removed the inductors and used a zero ohm resistor to verify that each inductor is not the source of unwanted oscillations. I have also tried removing the 10uF tantalum decoupling caps to verify that ESR does not cause strange behavior.

I was very disappointed to find that there was no SPICE model of the ADA4941-1 available for download from the Analog Devices website. However, I have derived some comfort from the fact that the circuit is "validated."

After building this design, it was more than apparent that my actual circuit had a very limited slew rate.

(1) The circuit diagram (Figure 1 at the above link) shows two 100nF (0.1uF) caps attached to nodes Voffset1 and Voffset2. What is the design purpose of these capacitors? I've found that the presence of these capacitors caused the output of the ADA4941-1 to be extremely distorted.

(2) I've used a 2V p-p sine wave as input to the ADA4949-1. At a frequency of 1kHz, there is very little distortion. However, as I increase the frequency to 10kHz and to 100kHz, the output wave "shrinks" and becomes increasingly attenuated around the common-mode voltage of

2.5V. Waveforms with > 2V p-p are attenuated, and the peaks are sometimes distorted, even when the voltage offset on my function generator allows for the peaks and troughs to be positive voltages. I am using +7V and and -4V power rails.

What is the best work-around for this type of circuit behavior? What is the most probable cause?

Nicholas

Reply to
Nicholas Kinar
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The 20 ohm + 2.7 nF loads look radical for this part. It's rated for a

20 pF load and can drive 25 mA typ.

What values of R2 and Cf are you using?

Are you sure you have it hooked up correctly? The observation about the 100 nF caps causing distortion doesn't make sense.

What is your bandwidth goal?

John

Reply to
John Larkin

Hello John--

Thank you for your response!

Hmm...it is a bit interesting indeed to see these component values being used after the op amp. Apparently the manufacturer thinks that this RC filter is the most effective way to prevent anti-aliasing for the ADC.

R2 = 1k and Cf = 10pF. To me these values don't seem to be too much out of the ordinary, since (1/(2*pi*R2*Cf)) = ~16MHz

I agree that it's very bizarre behavior. I've checked my circuit diagram, and it *appears* to be correct.

If this was only one part, I would have said that it could be a faulty component. But the same thing is happening for six of them!

The ADCs have a maximum sampling frequency of 400kHz.

Nicholas

Reply to
Nicholas Kinar

h out

25mA / 2.7nF =3D 9.2 V/uS

In the simplest case, this and not the 22V/us is the controlling factor on the slew rate. The distortion vs load curves make me suspect that you should not expect anything near 25mA out of the part without developing a distortion problem.

Reply to
MooseFET

That's an interesting prospect. I will try removing these caps on the output and see what happens.

Thanks Ken!

Reply to
Nicholas Kinar

Well, I removed these 2.7nF capacitors, and the output signal looks clean. Apparently the problem was indeed caused by these caps on the output!

I am now going to try replacing the caps on the Voffset1 and Voffset2 nodes, and I will see what happens when these become 0.1uF. (I'll post back here soon.)

Many thanks for your suggestions! Thank you John and Ken for your help!

Reply to
Nicholas Kinar

In my circuit, the much larger caps (0.1uF) still cause distortion when connected to the Voffset1 and Voffset2 nodes. However, using smaller caps (in the pF range) do not cause much distortion.

So this suggests that the distortion problems with my circuit were caused by the RC filter caps on the output and by the caps on the voltage offset nodes.

I suspect that the distortion problem created by the caps on the voltage offset nodes may be due to my own PCB layout. It appears that perhaps my PCB layout requires lower capacitance values than the one created by the engineers at Analog Devices. Another possibility is that the bandwidth requirements of the suggested circuit are much less than the bandwidth requirements of my own version of the circuit.

Nicholas

Reply to
Nicholas Kinar

So now the problem has been solved of excessive distortion on the output of the ADA4941-1.

However, I have noticed that some *slight* distortion is occurring at the bottom of the output waveform. The 2.7nF caps on the output have been removed.

Using a function generator, I've created sine, ramp, and square waves as inputs to the ADA4941-1 circuit. I've noticed that the peaks of the sine, ramp, and square waves are very clean. However, the troughs of these waves are slightly "skewed." The "skewing" seems to occur at higher frequencies (20kHz)

What could cause this skew? How might I modify the circuit to fix this small problem? Has anyone seen anything similar?

Nicholas

Reply to
Nicholas Kinar

In addition, if I wanted to add an RC filter on the output of the ADC input buffer, what would be the the most appropriate values for the resistor and capacitor? The maximum sampling rate of the ADC is 400kHz. I would like to maximize the operating bandwidth of the input buffer circuit, given the sampling rate of the ADC.

IMHO, the circuit shown here does not have very optimal values, at least for my application.

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Nicholas

Reply to
Nicholas Kinar

I'd also be worried about the amps oscillating with this much capacitance only 20 ohms away.

John

Reply to
John Larkin

Infinite caps on those + inputs should be fine.

I suspect oscillations caused by those absurd output lowpass filters. Once an opamp starts oscillating, all sorts of crazy things happen.

Analog Devices claims that this is a "verified" circuit? It was clearly hacked by a beginner who didn't even read the datasheet carefully.

John

Reply to
John Larkin

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What are the 0.1uF caps connected to? I'm wondering if there might be some fragmentary signal components on the "ground/supply" side of those caps. Especially if this is a layout of your own design?

Reply to
cassiope

Hello John--

Once again, thank you so much for your response!

Yes, apparently it was a "verified" circuit. I was a bit dubious about using this, and I had initially thought about rolling my own solution. On the same PCB (less than 2 inches away), I am using two op-amps to convert another single-ended signal into a differential one. You know what - it works quite well! There's also no distortion! I did the design and layout of that particular circuit.

So much for using "verified" circuits.

Reply to
Nicholas Kinar

The 0.1uF caps are connected to an AGND plane which is on the top side of the PCB. The AGND surrounds the op-amps and some other passive components. This ground plane is connected to another buried ground plane within the PCB. Both ground planes are joined by numerous vias.

Could I safely remove these caps? At the moment, I can't really think why they would be required.

Nicholas

Reply to
Nicholas Kinar

Yes, most of the oscillations are gone when the caps are removed. Could I still use the RC filter? What could be the most appropriate component values to use?

Reply to
Nicholas Kinar

One caution: most modern ADCs kick out a big zot of charge when they digitize. If an opamp is connected directly to the ADC, some opamps get seriously freaked out by that zot and take a long time to recover. Hence the RC after the opamp. But the values have to be right; too little R can make the opamp unstable and not isolate the zot; too much can produce ADC offset errors.

John

Reply to
John Larkin

Why have two planes if they're heavily connected?

They hold the opamp + inputs stiff. Without them, capacitive couplings inside the amps (like from supply rails) might mess up the frequency response a little.

They shouldn't cause problems. The problems are elsewhere.

John

Reply to
John Larkin

Something like 200 ohms or so should be OK. You really should keep the RC, as noted in my other post.

John

Reply to
John Larkin

Many thanks for this observation, John! I had attempted reading from the ADCs followed by the suggested RC filter, and I was wondering why the values looked like noise riding on the top of a perpetually-high signal. This provides a good explanation for what I've been observing. Obviously some tinkering is required to select the proper values.

Reply to
Nicholas Kinar

Erm, well - I don't know if this is a good explanation, but the reason is really due to space. There's no space for having a single GND plane for the entire PCB, since the top layer is pretty well stuffed full of components. The idea is to have the top AGND plane act as a Faraday shield for the more sensitive parts of the circuit. The buried AGND plane connects with a buried DGND plane at one point only. It is my hope that connecting the two planes with many vias will help to eliminate/reduce ground loops.

Yeah, I agree.

Hmmm...I am going to have to do a little bit of sleuthing. Thank you once again for your help, John!

Nicholas

Reply to
Nicholas Kinar

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