negative voltage generator

If you look closely, you'll see that the power supply ground is a little higher than the op-amp ground.

Cheers

--
Clive

"Modeling" current source I2 on page 17 of the datasheet as a literal ideal constant current source would explain the symptoms I think

Er I3, rather

I think my monitor has a ground loop.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Apparently no one is noticing the output is below ground.

Is the ad8034 available in LTspice XVII or is that an outside part?

Do any other LT op amps do the same thing?

What is the voltage on the negative input of the op amp? If the input pins are not clamped, I would expect to see +7.5V - input bias current.

How does the output voltage change when you change the applied input voltage?

What is the output impedance?

Why does an "input stage" diagram include the output?

Yeah, with no power supplies in sight this opamp generates voltages and currents. I suppose that ADI rushed to get their models into LT Spice.

This matters to me. I designed an ideal-full-wave-rectifier signal detector, based on these amps railing to ground, and it's off at low levels. I guess that with a bipolar output stage, I'd get some small (positive) offset anyhow.

The error is pretty small, better than just using diodes, so I might still do it.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Well, that was my point.

It's built into the opamp list now, with most of the other ADI parts. That's good.

Don't know.

Yup, 7.466.

Don't know.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

LTspice XVII won't run on XP, although it runs fine in Wine.

Thanks for the reply. I think you already pinpointed the problem as a bad model.

Huh, I had to stare at that for a minute or so till I figured out how it worked. Is there some reason you don't put a diode in the feedback loop? You can make an 'ideal diode' that way too.

George H.

Is this still in Beta? Got bugs? Is it worth changing over from IV yet?

-- This message may be freely reproduced without limit or charge only via the Usenet protocol. Reproduction in whole or part through other protocols, whether for profit or not, is conditional upon a charge of GBP10.00 per reproduction. Publication in this manner via non-Usenet protocols constitutes acceptance of this condition.

BTW as far as I read the LTSpice license agreement you wouldn't be violating their EULA by, if feasible, busting the encryption on the device model files to take a look or even port them to other Spices via a "clean room" behavioral re-implementation.

The EULA says IIRC something to the effect that you are prohibited from altering, reverse-engineering, decompiling, or modifying the binary LTSPice executables or models. An encrypted plaintext Spice model is not a binary nor executable code there's nothing to decompile or reverse-engineer. And decrypting the model files does not alter or modify the device models themselves in any way.

Fun. Dos the AD8034 unstick nicely from the rails?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

Version 4 is no longer being maintained. I suppose one could use it with the newer libraries--it's nice having those AD models built in.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
http://hobbs-eo.com

I don't know that "rushing" was necessarily the cause, it may be that they know encrypted models are security-thru-obscurity and can probably be cracked and don't want to risk giving away their super-duper-secret-sauce current source topology at a transistor-model level. But it's probably also hard to make a behavioral source that respects all goofy edge cases without giving away IP.

Best to make it obviously broken with a simple model as in this example here than insidiously broken with a complex one. You know. They know. They know you know. They aren't talking

CMOS op-amps rail nicely. That, or feed the AD8034 a bit of negative juice?

Cheers, James

It could be argued that since ASCII is a binary representation of text, and that the model are unintelligible to humans the models are acutally binary. Your best be may be to move somewhere where that part of the EULA is uninforceable.

--
     ?

I'll need other 8034s on the board, so it's the preferred choice. They come off the rails beautifully, perfectly usable as a comparator. I'm not at all complaining about the opamp, I'm complaining about the unreality of the Spice model.

A fullwave detector+filter, made from rrio amps without diodes, should be pretty good with signal levels from ten volts to maybe 10 millivolts. I'm designing a simuator of capacitive tank probes, and I want to build in a good AC voltmeter circit for self-test, and to let the customer remotely measure his excitation voltage (and frequency.)

I could just digitize the sinewave waveform and do math on the samples. My firmware guy would complain but he'd do it. The problem there is to pick a sample rate that doesn't heterodyne with the basically unknown customer-provided excitation signal, which is a non-trivial problem. An analog detector avoids those issues.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Hah, mine is 20 times better than yours--try replacing the built-in model with the earlier AD pspice model below. Minus 680 mV. ;)

Cheers

Phil Hobbs

===============

• AD8034 Spice Model

• Description: Amplifier

• Generic Desc: Dual 85MHz FET Input Amplifier

• Developed by: TRW

• Revision History: 08/10/2012 - Updated to new header style

• 3.0

• Copyright 2002, 2012 by Analog Devices, Inc.

*

• Refer to
  formatting link
  for License Statement.

• Use of this model indicates your acceptance with the terms and provisions in the License Statement.

*

• BEGIN Notes:

*

• Not Modeled:

• Distortion is not characterized

*

• Parameters modeled include:

• closed loop gain vs. frequency

• output clamping voltage and current

• input common mode range for FET input

• input impedance

• slew rate

• output currents are reflected to V supplies

• Vos is static and will not vary

• Ibias current will remain around 50 pA over common mode range

*

• END Notes

*

• Node assignments

• non-inverting input

• | inverting input

• | | positive supply

• | | | negative supply

• | | | | output

• | | | | | .SUBCKT AD8034 1 2 99 50 30

• FET INPUT STAGE

Vos 9 2 1e-3 Ios 2 1 0.75e-12 Cd 1 2 1.7p Ccm1 1 0 2.3p Ccm2 2 0 2.3p J1 5 1 10 NMOD J2 6 9 11 NMOD R3 99 5 1132 R4 99 6 1132 R5 10 4 1020 R6 11 4 1020 I11 4 50 225u

• GAIN STAGE & POLE AT 2.47 kHz Eref 15 0 POLY(2) 99 0 50 0 0 .5 .5 G1 13 15 5 6 1 R7 13 15 28k C3 13 15 2.3n V1 98 14 0.12 V2 16 52 0.12 D1 13 14 DX D2 16 13 DX

Ecc 98 0 99 0 1 Ess 52 0 50 0 1

*POLE AT 350 MHz G2 15 43 13 15 440e-6 R10 15 43 2.27k C5 15 43 0.2p

*POLE AT 425 MHz G3 15 53 43 15 534e-6 R11 15 53 1.87k C6 15 53 0.2p

*POLE AT 834 MHz G4 15 63 13 15 628e-6 R12 15 63 1.59k C7 15 63 0.12p

• BUFFER STAGE Gbuf 15 32 63 15 1e-3 Rbuf 32 15 1000

• OUTPUT STAGE Vo1 99 90 0 Vo2 51 50 0 R18 25 90 .04 R19 25 51 .04 Vcd 25 30 0 G6 25 90 99 32 25 G7 51 25 32 50 25 V4 26 25 -0.846 V5 25 27 -0.846 D5 32 26 Dx D6 27 32 DX

Fo1 15 70 vcd 1 D7 70 71 DX D8 72 70 DX Vi1 71 15 0 Vi2 15 72 0

Erefq 96 0 30 0 1 Iq 99 50 3.08m Fq1 96 99 POLY(2) Vo1 Vi1 0 1 -1 Fq2 50 96 POLY(2) Vo2 Vi2 0 1 -1

.MODEL NMOD NJF VTO=0.222 BETA=100 IS=1.27e-15 .MODEL DX D(IS=1e-15) .ENDS

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
https://hobbs-eo.com