Multiplexer sample and hold

Just an aside, I have a stock of a bunch of polystyrene caps I bought several years ago for some reason. They're quite physically large for the capacitance they provide, but they are pretty good at having close to ideal properties

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snip aside

I have not found it so -- compare the cost of good capacitors with the cost of good DAC channels and make your own conclusions, though.

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Will do. For the thing I'm thinking about I think I would need on the order of a dozen outputs.

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The under 1000pF region would let you use C0G caps, which are inexpensive and don't have a D.A. distortion problem.

I've analyzed it for some Arduino controllers, with limited PWM output lines (and also in applications where I've used most of the pins). You set an interrupt at the end of each PWM cycle, and change the multiplexer switch and change the PWM setting to the next channel before restarting the timer.

If you increase the PWM timer input clock to 1MHz,

and are using 8-bit PWM, each PWM cycle takes 256 us. Using an 8 channel multiplexer, the period time is 2ms, and you need a say 10 to 20ms filter on each channel. Some may like the idea, but I wasn't encouraged.

With PWMing, there's always a speed / resolution tradeoff.

There are several ways to improve the speed and resolution of the PWMing. One is to dither (change the PWM level by one LSB, over a number of consecutive PWM-channel periods), ST's AN4507.

argg, what a painful link!

Another is to use two PWM channels, and combine them with resistor ratios. This is possible because the MSB channel has perfect single LSB steps, due to the crystal clock.

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Another option to deal with inadequate PWM channels is to add a multichannel PWM chip. These are popular because they're so useful with LED displays. E.g.,

NXP's PCA9635, 16 bits, 16 channels LTC's LT8500, 12-bits, 48 channels

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That's not common any more. Charge injection and drift limit accuracy, and buffered multichannel DACs are small and cheap.

We sometimes make slow DACs from one pin of an FPGA, delta-sigma and an RC lowpass filter. That's an alternate to PWM. I guess that software bit-bang delta-sigma is not a totally crazy idea.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics

It works fine where you only need "DC" or low frequencies. Then you can use a NPO and quite a high value (10-100nF say).

I used it for a 8-channel 0-10V output where it was just going to a PLC monitoring slow process variables. There was an IRQ that drove the 4051 address lines and updated the next output, every 100us or whatever.

I don't know why the hardware is not more common to do that, in microcontrollers. PWM can be extremely accurate. Market it as a 24 bit DAC.

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John Devereux

Sure it works, but is it sensible to replace one octal DAC chip with a DAC, a mux, eight caps, and eight opamps? Less often than in the past.

PWM has some ugly tradeoffs between speed and accuracy.

It does seem like uP PWM blocks could add a delta-sigma mode with a tiny bit more silicon, but accuracy will still be limited by ground loops and Vcc accuracy and stuff.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Why does NPO matter here? You have a reset every few milliseconds, anyhow, and it's hard to believe there's any microphonic problem or drift issue.

More to the point, if you're gonna do a dozen of these, why not pester the manufacturers to come up with a purpose built track/hold chip, it just takes plus/minus power, capacitor, input, output, and strobe. That way, the leakage and pickup on the full mux-to-amp trace doesn't noise up the output. As I read it, that trace is just floating most of the time.

Other ceramics suffer from dielectric absorption which will totally screw a S&H.

The issue is still the cap. Why go to the bother of all that, instead of just building more ADCs? Pins are expensive. Transistors are free.

Dielectric absorption is a problem for monostable reset (and in dual-slope converters), but not for a filter cap that regularly gets updated from a reference.

If it's being charged from a fixed voltage, why do you need a S&H?

Because the source spends most of its time in a high-impedance state. Wasn't that clear from the original question and discussion?

Is sample and hold still used for ADC?

Yes. I've used it in a design where we saved a great deal of money doing that. I have also used a simelar technique to reduce power consumption of a reference using S/H low current amp.

Cheers

Klaus

If you don't care about the results, don't measure anything. I like your minimalist attitude.

Well the DAC was free, and it would need to be a "high voltage" octal DAC.

I usually run it through external tinylogic gates powered from the precision supply. Or make it drive an analog switch that alternates between ground and the supply.

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John Devereux

I have a medical application chip design where the bandgap is fired up, sampled-and-held, then put back to sleep, to significantly save power. ...Jim Thompson

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