RCD snubber from drain to ground helps. If you use a dV/dt snub (small capacitor, small R*C time constant), you can slow down the edge, saving switching losses in the transistor and absorbing the overshoot.
If you use a peak snub (large C, enough R to maintain DC level), the overshoot spike is clamped, dumped into the capacitor, and dissipated as heat in a dumb resistor rather than sensitive transistor junctions.
Note that a dV/dt snub carries load current while the voltage swings by. This doesn't allow the stray inductance to discharge, so you still get overshoot. To minimize overshoot, you need a much larger dV/dt snub than otherwise, or you need a peak snub as well.
Switching transient with dV/dt snub, circuit:
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Waveform:
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Top: voltage, bottom: current 1A/V (-4 offset).
- Switch on: current blip due to diode capacitance, represented by C2. Small ringing is due to the inductance between transistor, diode and output load (the 36V supply), represented by L2. This series resonant circuit is damped by Q1's Rds(on), V3's internal resistance (typically capacitor ESR), and any loss components in the circuit (R4 in this case).
- On state: current rises; a lot of nothing else happens.
- Switch off: drain voltage rises and current falls. D2 turns on and C3 charges. Load current is transferred to C3. Technically, this waveform is described not by a triangular slope, but by a fraction of the resonance between L1 and C3.
- Damped "bouncing": as voltage rises past V3, D1 turns on and L2 charges up. Now, the waveform is described by the resonance of C3, L2 and R4. Voltage continues to rise, humps over, and falls. As the voltage falls, L2 discharges and D1 switches off. Now it goes back to the L1-C3 resonance, which makes a short spike before D1, L2 clamp it again. This repeats until the oscillation amplitude is less than Vf, at which point D1 remains on and D2 remains off; the remaining oscillation is damped by R5. This occurs after about two negative-going spikes in this case.
Ringing is well damped by R4, for simulation stability and clarity. Since, in practice, this inductance is due to stray distance between components, it is difficult to dampen directly. An alternative is an R+C damper across the capacitance, in this case D1 and Q1, to dampen the falling and rising edges, respectively.
The equivalent, applied to your circuit:
- L1 + R1 represents the load current, which in this case is delivered by transformer. During the switching transient, it can be assumed reasonably constant.
- Everything past the MOSFET and snubber is behind a transformer, so making certain connections becomes dubious (e.g., placing R4 across only the leakage inductance of a transformer!)
- L2 represents the leakage inductance of your transformer.
- V3 is the voltage which the waveform transitions to after the switching event; since you're driving nearly full duty cycle into a PP transformer, this is the opposite side MOSFET (and its body diode), which in this circuit, is simply twice the supply voltage.
The magnitude of all components can be estimated from circuit geometry and component measurements (you'll likely have to measure your transformer).
- C3 is calculated based on either the load current, delta V and desired rise time (usually 50ns to 5us depending on use; for under-100kHz stuff,
200ns or so is fine), or the desired damping characteristics.
- You want the snubber to discharge appreciably while the transistor is on, so you want 3 * R5 * C3 = t_on(min). This simulation used t_on = 10us, so I picked 5us, close enough. I picked R5 somewhat large to illustrate the type of nonlinear ringing you get from an underdamped diode type snubber.
The waveforms with a peak voltage snubber look similar, except:
- Rising edge is fast (obviously, it's normal)
- A fast ringing overshoot spike, determined by MOSFET-diode-capacitor path inductance as the snubber diode "grabs" on
- "Top" voltage is determined by the capacitor, looking like a 1/4 sine wave (relatively small capacitance) or a flat clamped flyback pulse (high capacitance limit)
- When the leakage is done discharging, voltage relaxes back to its steady value (i.e., the opposing half of the square wave), with ringing determined by stray (diode and transistor junction) capacitance.
Tim
--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
"P E Schoen" wrote in message
news:jqraib$jm0$1@dont-email.me...
I had posted about success with fast MOSFET gate drivers on my 1500 VA DC-DC
converter. The UCC27321 drivers provide up to 9 amps so the MOSFETs now
switch on and off very quickly compared to the previous drivers, which were
actually gates of an LM324 op-amp. So, although I got better efficiency and
I was able to apply 25 VDC, the 30 volt TVS diodes from each drain to the 25
volt supply overheated, and I removed them.
The output waveform of the transformer was a very clean square wave with a
little bit of ringing during the 1 uSec dead-time transition, but the drain
waveform showed very high spikes at the transition. I was able to reduce the
amplitude somewhat, by adding a capacitor across the drains, as well as a
snubber, but one of the MOSFETs failed shorted. It was probably damaged
before I added the snubber and capacitor. But even after I replaced it, and
I added capacitors from drain to common, there were still unacceptably large
spikes, especially as I increased the voltage from my power supply.
There is also certainly a large current spike due to the load capacitors
being charged with a square wave, but I do have a 100A 100mV shunt from the
sources to common, and an external interrupt that should shut down the PWM
if the current is greater than 100A, but it could easily be much higher
before the PWM removes the gate drive. And then there would be a much larger
dead time. The MOSFETs are HUF75645 which are rated at 100V and 75A
continuous, and at least 450A pulse current for 10uSec. Turn on and turn off
times about 200 nSec. I have two in parallel on each leg of the push-pull.
So, I'm looking at ways to minimize these high voltage transients without
reducing efficiency too much. Some ideas are:
1. Adding capacitance to maintain the current flow through the inductor
during transition. This may be most efficient, but it will cause a lot of
ringing. And the capacitors need to be able to carry the maximum current of
the transformer primary, which could be as high as 50 amps or so. Maybe a
lot more if the current is reflected from the output capacitor charging.
2. Using RC snubbers to limit the peak voltage as well as dissipate the
energy in the resistor. I have tried a single snubber of 0.047uF and 2 ohms
across the primaries, which helped a little. But from my simulation it
seemed like it might be better to add snubbers across the D-S of each
MOSFET. Not really sure of the component values. For 50A peak the 2 ohms
will limit the spike to 100V. That's 5000W but only for less than 1uSec out
of a 250uSec pulse (2 kHz), so average power is about 5000/250 = 20W.
Probably much less.
3.Using TVS diodes to limit the voltage spikes to, say, 80V. The TVS diodes
I used were two 15V in series, so they were trying to suppress the spike at
a lower voltage than necessary, so they got hot. And that was before the
capacitors and snubbers. Probably a good idea to add them, and then design
the snubbers to keep them from absorbing any more than occasional spikes.
4. Slowing down the transitions of the gate drives. These high spikes seemed
to appear after I added the fast gate drivers, and the previous slower
drivers seemed to work well enough, although not as efficiently. So I can
probably add resistance and capacitance to cause slower turn-on and
turn-off, which will essentially quench the inductive spike in the MOSFETs.
Also reduced efficiency, but easier to dissipate the heat in the large heat
sinks than much smaller TVS diodes or snubber resistors.
I'm going to research some of the application notes on MOSFETs and gate
drivers, but some discussion would be appreciated. At least this is actually
about some "cool" electronics and not OT squabbling.
Thanks,
Paul