Metastability in Flip Flops

hi, how can we explain the metastability(first of all what is metastability)in flip flops when set up /hold time is viloated.(cosider flip flop architechture using pass transistors and inverters.)

Rgds, Sreenath.

Reply to
Sreenath
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Gremlins.

Robert

Reply to
Robert

There are plenty of papers on the subject. Go into google scholar and seach flip flop metastability.

Reply to
miso

... why would "we"?

Reply to
Frithiof Andreas Jensen

Flip-flips are bistable structures, If you bias the input at exactly the right voltage at exactly the right time, you can set the latching transistors exactly at the point where there is no preference for one state or the other. This state is - of course - unstable, but the structure can take a very long time to fluctuate about this "metastable" point to one side or the other to the point where it will move progressively more rapidly to one or other of the stable conditions.

In practice, if the latching structure is set close enough to the metastable point that the nett current available to charge up the transistor capacitances involved isn't high enough to allow the transition to an outptu state within the guaranteed propagation time of the device, people start talking about meta-stability.

See if you can find (or make) a device level Spice model of a flip-flop, and have a play with that,

--
Bill Sloman, Nijmegen
Reply to
bill.sloman

Its like trying to balance a pencil on its point, the closer you get it to its vertical the longer it will take to fall over and the more the uncertainty wich way it will go.

Likewise the closer the edge of the set input to the clock edge the more uncertain is the output and the longer it takes to settle to a defined state.

Colin =^.^=

Reply to
colin

Hello Bill,

And I thought they were sandals ...

--
SCNR, Joerg

http://www.analogconsultants.com
Reply to
Joerg

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