LTSpice question

I would like to determine the overall response of a LC circuit where the L value is stepped and the C value is stepped for each L value and the overall response is displayed in dB..

In Basic it would be:

For L= 1 to 100 step 10 For C=1 to 100 step 10 Print response next C next L

Any idea how to do that?

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Reply to
billbowden
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Good question. Take a look at the ".step param X list" shown in the LTSpice code at the bottom of Helmut's post #3:

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Thank you,

--
Don Kuenz KB7RPU
Reply to
Don Kuenz

I know you can step in two variables, but I don't remember exactly how to do that. I've used the variable step function before and the hard part is being able to see the results. I don't recall ever seeing a way to get LTspice to print results except in a rather clumsy way to a popup window. I normally graph the results. If each pass gives a single value, that could produce multiple curves, all the points on a curve for one parameter and the different curves for the other.

There is a Yahoo group that is a treasure trove of information. The help files have a lot of info, but requires careful reading to get it right. Helmut is normally the guy who answers all the questions there. Really knows his stuff. A search of the conversations and/or files will almost certainly turn up exactly what you need without posting yourself.

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Rick C
Reply to
rickman

Sure...wouldn't it be nice to have GUI setups for multi-variable sweeps, and automatic display of the results. :-)

-- Kevin Aylward

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- SuperSpice
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Reply to
Kevin Aylward

Spice is essentially a command line program. LT gave it a schematic interface and ways to embed your commands there. That's not too shabby. If I used it more often than a couple times a year I might remember how to do some of this stuff. lol

When I have a real need I dig in and relearn how to use some of these fancier features. It's a pretty popular program and there are lots of tutorials about it, both written and video.

I was struggling with adding a model the other day and couldn't get it right. There are three parts, the symbol, the model and the schematic where it is used. I thought the problem was in the model (off the web along with several forum posts about how to "fix" it) or the schematic. Then I found this exact model in the LTspice group and it still wouldn't work. Turns out I hadn't downloaded the symbol and mine was getting used, so then I knew where the problem was. I messed up the pin order. If I hadn't found these example files in the Yahoo group I might still be fighting it.

--

Rick C
Reply to
rickman

,

I suspect Kevin was hinting at his SuperSpice ;)

Reply to
Lasse Langwadt Christensen

Indeed. Not sure if he cottoned on or not.

The LTSpice engine is fast and converges extremely well, but it is a huge pain to actually use, imo.

I still cant get over how its help describes the non-standard GUI operation mode, as an advantage, to wit, you cant just mouse grab and move components.

In my daily i.c design work, I use SS to free up Cadence licenses. I use it extensively for multi-run Worst Case corners. It is simply not practical to use LTSpice for that.

-- Kevin Aylward

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- SuperSpice
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Reply to
Kevin Aylward

Indeed. He seldom misses the chance.

Reply to
Cursitor Doom

Look in help for the .STEP command.

Reply to
John S
[snip]

Absolutely!

Sno-o-o-ort >:-} The "GUI" is horrible... worse even than Cadence Virtuoso Composer, which I absolutely hate.

I only get exposed to LTspice because my behavioral modeling customers require that the models run on LTspice.

I handle that by designing/developing in PSpice, then running the resultant .CIR file in LTspice to verify that the model will work under LTspice.

This will run in LTspice (once you create it in PSpice O:-) ...

.PARAM VDD={ROW1+ROW2+ROW3+ROW4}

  • B1V8={IF(CASE==3,1,0)+IF(CASE==4,1,0)}
  • S3V3={IF(CASE==2,1,0)+IF(CASE==4,1,0)}
  • CASE=1
  • PVDD=0 ; 0=TYP, -1=MIN, 1=MAX
  • ROW1={IF((CASE==1)&(PVDD==0),3.3,0)+IF((CASE==1)&(PVDD==-1),2.5,0)+IF((CASE==1)&(PVDD==1),3.6,0)}
  • ROW2={IF((CASE==2)&(PVDD==0),2.5,0)+IF((CASE==2)&(PVDD==-1),2.35,0)+IF((CASE==2)&(PVDD==1),2.75,0)}
  • ROW3={IF((CASE==3)&(PVDD==0),3.0,0)+IF((CASE==3)&(PVDD==-1),2.7,0)+IF((CASE==3)&(PVDD==1),3.3,0)}
  • ROW4={IF((CASE==4)&(PVDD==0),3.3,0)+IF((CASE==4)&(PVDD==-1),3.0,0)+IF((CASE==4)&(PVDD==1),3.6,0)}
  • VDDIN={(1-B1V8)*VDD+B1V8*1.8}
  • RISING=0
  • EN=1 ...Jim Thompson
--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

     Thinking outside the box... producing elegant solutions.
Reply to
Jim Thompson
[snip]

This will run in LTspice (once you create it in PSpice O:-) ...

Yeah....but agro... :-)

What I cant understand, is why there isn't direct support for WC and MC in LTSpice like

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Cadence has an even more extensive support for those features. All pro gear does.

IC design mandates such runs. You just cant do a tapeout without doing all the process corner checks. I might do 100,000 runs for a chip design.

I have always assumed LTSpice was the engine LT used for their own chip design, and just popped it out to the public as a side line. If so, it would have to have WC/MC built into it, but so far, I am not aware of any "undocumented" features implementing it.

Oh yeah again, for any one reading. I finally got around to implementing the LTSpice "VDMOS", but just to annoy Mike, I made it "better". This is the non-linear cap stuff to MOS 1 models. It has non-linear caps for both CGS and CGD, also a subthreshold extension and Quasisat. This is for those Audiophile designers..

I added an internal RG gate resistance to the model as well. This is an interesting one really. The original implementation only has RD and RS. The rational for this seems to be that, in a pure mos asic digital design, mos drains feeds the gates of another mos, essentially as a constant current via its gm. This means RG isn't that important in that situation. For a discrete Mos, it has a major effect though.

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-- Kevin Aylward

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Reply to
Kevin Aylward
[snip]

I suppose it's possible that LT uses LTspice as their "engine", but I'd guess at least some kind of Cadence front-end. Wouldn't surprise me if they actually use all Cadence tools for their internal design work.

Yep. If you understand how things actually work, it's relatively easy to write your own models... I did a gate-charge subcircuit add-on around 1990 to make the crude existing models behave more realistically.

Of course there are some "physicists" lurking here that think diode turn-on overshoot can't be modeled without tinkering with the "engine"

...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

     Thinking outside the box... producing elegant solutions.
Reply to
Jim Thompson
[snip]

I would have thought so. At TI is was all Cadence, accept for the transparent integration of TISpice instead of Spectre.

Other than Mentor, it would be insane not to use Cadence. There really isn't any other viable solution.

Yes. Indeed.

I do still have have a .subckt cgs model in my SS libraries, its just that I finally got off my arse and put it directly in the XSpice code. It was trivially easy once I actually had a look at the code. It basically had a switch section where you put in any formula you want. It was harder to insert RG. Had to figure out how to add the extra entries in the varies dc and ac matrixes setups and node allocations. You do have to understand something about electrical matrix theory to do this, its not just software.

subckts with behavioural expressions can be very powerful.

-- Kevin Aylward

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Reply to
Kevin Aylward
[snip]

My point exactly. I just wrote one for a 12-bit string DAC with a one-layer vernier, all parameterized, so the customer can completely evaluate resistor and switch values before actually committing to device level... total time, 2 days ;-) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| STV, Queen Creek, AZ 85142    Skype: skypeanalog |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 

     Thinking outside the box... producing elegant solutions.
Reply to
Jim Thompson

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