I'm trying to add the models of a couple of N-FETs I use to LTSpice. I'm getting a simulation-time error that I can't resolve. Any ideas? Thanks.
The error:
|M1: Only a level 9 B3SOI can have 6 nodes
It thinks I have six terminals on my transistor and only SOI models have that many? Looks like only three to me.
The circuit:
Version 4 SHEET 1 880 680 WIRE 144 -80 16 -80 WIRE 288 -80 144 -80 WIRE 16 -32 16 -80 WIRE 144 0 144 -80 WIRE 288 16 288 -80 WIRE 16 80 16 48 WIRE 288 112 288 80 WIRE 144 192 144 80 WIRE 240 192 144 192 WIRE 144 240 144 192 WIRE 288 288 288 208 WIRE 288 288 208 288 WIRE 288 320 288 288 WIRE 144 448 144 336 WIRE 224 448 144 448 WIRE 288 448 288 400 WIRE 288 448 224 448 WIRE 224 496 224 448 FLAG 224 496 0 FLAG 16 80 0 SYMBOL LED 272 16 R0 SYMATTR InstName D1 SYMBOL npn 208 240 M0 SYMATTR InstName Q1 SYMBOL res 272 304 R0 WINDOW 0 -7 51 Left 0 SYMATTR InstName R1 SYMATTR Value 100 SYMATTR SpiceLine tol=1 pwr=0.1 SYMBOL res 128 -16 R0 SYMATTR InstName R2 SYMATTR Value 10K SYMATTR SpiceLine tol=1 pwr=0.1 SYMBOL voltage 16 -48 R0 SYMATTR InstName V1 SYMBOL DiodesInc\ Models\\DMG1012T 240 112 R0 SYMATTR InstName M1 TEXT -18 520 Left 0 !.op
The model:
*SYM=POWMOSN .SUBCKT DMG1012T D=10 G=20 S=30- TERMINALS: D G S M1 1 20 3 3 NMOS L=0.6U W=47.66m RD 10 1 220m RS 30 3 80m CGS 20 3 57p EGD 12 0 20 1 1 VFB 14 0 0 FFB 20 1 VFB 1 CGD 13 14 27p R1 13 0 1.00 D1 12 13 DLIM DDG 15 14 DCGD R2 12 15 1.00 D2 15 0 DLIM DSD 3 10 DSUB .MODEL NMOS NMOS LEVEL=3 U0=500 VMAX=80k
- ETA=0.1m VTO=0.99 TOX=16.8n NSUB=4.57e16 .MODEL DCGD D CJO=27p VJ=80m M=0.320 .MODEL DSUB D IS=36.1n N=1.50 RS=21.8m BV=20
- CJO=14p VJ=0.800 M=0.420 .MODEL DLIM D IS=100U .ENDS
Another model with the same problem:
.SUBCKT irlml6402 1 2 3
**************************************- Model Generated by MODPEX *
- All Rights Reserved *
- UNPUBLISHED LICENSED SOFTWARE *
- Contains Proprietary Information *
- Which is The Property of *
- SYMMETRY OR ITS LICENSORS *
- by Symmetry License Agreement *
- Model generated on Sep 25, 06
- MODEL FORMAT: SPICE3
- Symmetry POWER MOS Model (Version 1.0)
- External Node Designations
- Node 1 -> Drain
- Node 2 -> Gate
- Node 3 -> Source M1 9 7 8 8 MM L=100u W=100u .MODEL MM PMOS LEVEL=1 IS=1e-32
- Default values used in MD1:
- RS=0 EG=1.11 XTI=3.0 TT=0
- BV=infinite IBV=1mA .MODEL MD1 D IS=1e-32 N=50
- Default values used in MD2:
- EG=1.11 XTI=3.0 TT=0 CJO=0
- BV=infinite IBV=1mA .MODEL MD2 D IS=1e-10 N=0.4 RS=3e-06 RL 5 10 1 FI2 7 9 VFI2 -1 VFI2 4 0 0 EV16 10 0 9 7 1 CAP 11 10 9.68769e-10 FI1 7 9 VFI1 -1 VFI1 11 6 0 RCAP 6 10 1 D4 6 0 MD3
- Default values used in MD3:
- EG=1.11 XTI=3.0 TT=0 CJO=0
- RS=0 BV=infinite IBV=1mA .MODEL MD3 D IS=1e-10 N=0.4 .ENDS irlml6402