Lower time jitter in PLL

A pll output may have more or less jitter than the reference. It depends on the VCO and the filter.

What kind of VCO did you use?

John

Is 100kHz the bandwidth of your _loop_ or of your loop _filter_?

What you are reporting wouldn't be consistent given a loop bandwidth of

100kHz and measurement bandwidth of 10Hz. With a measurement bandwidth that is 1/10th your loop bandwidth I would expect the timing jitter of your reference to print right through to your output, which would cause the phase jitter to be multiplied by 8.

However, if you mean that you have a pole in your loop _filter_ at

100kHz, an actual loop bandwidth that's significantly lower than 10kHz (like, say, 5kHz), and a VCO that's really low noise, then I could believe your measurement.

Were I to get measured values like this I would suspect either my measurement or my loop bandwidth. I'd measure my loop bandwidth, I'd measure the open-loop jitter of my VCO, and if I couldn't get the facts to line up I may go as far as to make three doubler stages to get 80MHz from 10Mhz the old fashioned way, and measure the jitter of _that_.

--
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
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You haven't given the Q (damping factor) of your PI filter. Theres an optimum value, and if you haven't got enough damping the loop can ring, which does add jitter to the output of the voltage controlled oscillator.

The optimal Q does depend on the length of your divider - I was once involved in project where the designer had missed this, and correcting the oversight significantly improved our jitter.

Floyd M. Gardner's "Phase Lock Techniques" ISBN-10: 0471042943 ISBN-13: 978-0471042945 covers the theory involved, as do the application notes for the 4046 PLL chip.

-- Bill Sloman, Nijmegen

It is Minicircuits POS-150 (Kvco =~ 6 MHz/V). For Kvco=750 kHz, Kd=0.46 rad/V, wn=2*PI*100kHz, xi=0.7 calculated filter values are R1=1.2k, R2=510, C=4.7n (R2 & C are in feedback net). I used MCL RPD-2 phase detector and Sanyo LB3500 by-8 divider. Active PI filter is build on TI OPA27. My goal was to achieve quiet signal source at 80 MHz (this signal was a reference for another PLL). I didn't measured phase noise for freely running VCO, because phase fluctuations of VCO are not

Is the 100kHz just the bandwidth of the loop filter or the bandwidth of the whole closed loop?

Within the loop bandwidth, the noise of the VCO is substituted by the noise of the reference source, multiplied by the frequency ratio.

Jitter parameter is fairly meaningless. How does the phase noise look like?

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

Tim, please explain difference between loop bandwidth and loop filter bw. I know, that lock range and hold range of phase loop are strictly connected with loop filter bandwidth, but maybe I am not familiar with proper terminology.

I see now, that I made a mistake during writing my 1st post: measurement bandwidth was from 10Hz (lower limit of E4440A) to 100 kHz (1e5 Hz). But integrated PSD from 10kHz to 100kHz is quite low and those values are almost identical. So, timing jitter of my reference source should be reprinted by PLL to divided VCO signal, but phase noise of my VCO at 80MHz is 8 times grater, am I correct? And reference phase noise and divided VCO phase noise should be almost equal?

This is a cheap VCO from Minicircuits and it has much larger phase noise than reference. I think that I should check my circuits and repeat all measurements.

Could you tell me, which methods of "traditional" multiply give me best results? I 'discovered' that mixing reference signal with retarded copy of this signal can produce a sum frequency with lower phase noise at output of mixer. Using 3 mixers one can produce 80MHz from 10MHz quartz oscillator, but between stages signal must be amplified. This will degrade overall phase noise, since 1/2 of noise power inserted by amplifiers will be added to phase noise.

Thanks, E.C.

Hm, I am not sure now. I calculated loop filter using formulas from R. E. Best book, for given wn (natural frequency), xi (dumping factor) and Kvco,Kd.

I expected this kind of behavior.

Phase noise of 10 MHz reference and PLL output:

I made also measurements for different reference generator, I took 10 MHz from HP5334B counter:

In first example, reference signal was from E4440A signal analyzer. I tried to find phase noise floor of E4440A for 100MHz, but values in datasheet are only for 1 GHz carrier frequency (maybe those values can be rescaled for 100MHz by subtraction 20dB, I don't know)

E.C.

It's more than just terminology. From your response to Vladimir's post, it sounds like you're trying to apply a method by rote from a cook book, or worse you're taking a text book as a cook book and applying example results by rote.

You're implementing a closed-loop feedback system, like this drawing (view with a fixed-width font):

• ref ---->O---> loop filter ---> VCO ----o------> out - A | '------------------------------'

where the summing junction (the 'O') is your phase detector. The loop filter, _by itself_ will have some poles (usual practice is to use an integrator and some higher-frequency rolloff), and the VCO will act like an integrator. Once you close the loop those poles will move -- you'll still have the two or three significant poles that you started with, but instead of having two integrators at s = 0 and a rolloff, now you hope to have three stable poles that act in concert to make the loop behave like a low-pass filter with a gain of exactly 1.

Lock range and hold range are connected with the loop bandwidth, but the loop filter poles and gain is determined by the desired loop, so it's not clear which you're talking about. I _suspect_ that you mean loop bandwidth -- perhaps you should go back over the pertinent sections of your book and see if the author makes the difference clear?

Yes, kind of. If you are well within the bandwidth of your loop, and if your VCO noise is low enough to not contribute, yes. If your book is decent then it'll show you how to do these calculations from first principals. Basically at any given frequency your output noise will be some constant times your VCO noise and some constant times your reference noise. As the frequency gets close to the carrier the VCO constant will go down and the reference constant will go up in a predictable way -- but to really calculate the phase noise at the output you need to know the PSD of the noise from the VCO and the reference.

That sounds wise.

I'd have to sit down to do the analysis, which I'm not going to do for free on a newsgroup, but in general an amplifier can give you lower noise than an oscillator. If you _really_ wanted to get the noise down you'd amplify the heck out of the 10MHz reference with the lowest noise, highest power amplifier that you could get away with, run the result through a crystal filter, run _that_ through a varactor multiplier, and then use a multi-stage bandpass filter to pick out the 80MHz.

Even just amplifying at 10MHz and driving a diode multiplier from your reference, then filtering for the 8th harmonic should give you a clean, if low-level signal.

Neither of the above methods is a sensible way to design a product in

2008 (1968 maybe, but not 2008). But if you just can't trust your measurements, it may be a good way to verify the sanity (or insanity) of your test set up.

--
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html

- 480MHz is practical, if you can afford the ultra-thin crystal required - and divide it down to 80MHz using really fast logic - Motorola's (now ON Semiconductor) ECLinPS comes to mind. You can keep the jitter down to one or two picoseconds using this approach.

The temperature stability of the 480MHz source isn't great, but if you got a nominally 480MHz voltage-controlled oscillator, and used that as the VCO in a phase-locked loop you could lock the 480MHz source to a good 10MHz reference.

The 480MHz VCO can't be pulled over more than a 100ppm or so, so noise on the control voltage won't inject much phase noise into the oscillator output.

Could be a fun project ....

-- Bill Sloman, Nijmegen

used that as

Drat. Not a VCO but a VXCO - a nominally 480MHz voltage controlled crystal oscillator -see corrected text above. Visiting with my brother and drinking his excellent white wine has definitely reduced my attention span.

-- Bill Sloman, Nijmegen (but in Sydney at the moment)

Which book could you recommend me? In fact, I'm not an engineer, my specialization is optics, so I never needed to use Laplace transform and so on. I just need to build a reference source, which will be used in my experiment. If it will work, I probably buy a ready to use 80MHz quartz generator.

Thanks, E.C.

I suggest you start with the ARRL handbook, or the "Art of Electronics".

--
Tim Wescott
Control systems and communications consulting
http://www.wescottdesign.com

Need to learn how to apply control theory in your embedded system?
"Applied Control Theory for Embedded Systems" by Tim Wescott
Elsevier/Newnes, http://www.wescottdesign.com/actfes/actfes.html

If you are in a rush Digikey still has 17 of their P/N CTX179-ND. About six bucks.

I certainly understand your predicament. I had to do the opposite learning curve. A client wanted a complicated never-built-before laser diode control and I had to delve deep into optics, something I never had to deal with before.

The world I come from, this is a photon:

--
Regards, Joerg

http://www.analogconsultants.com/