Doing logic in the typical context of FPGAs and such is dead easy for the most part. Trying to make logic from gates is a PITA. I remember the days before HDL when we fought tooth and nail to keep using schematics. Lol, I wouldn't go back for love nor money now. Combine the inflexibility of gates with the LTspice GUI and you have a loose-loose situation.
What were you designing?