Logic circuits in LTSpice

When simulating purely digital circuits in LTSpice (with the exception maybe of pull-up and pull-down resistors, etc.) is it best to use the "standard" solver in the settings, or the "alternate"?

Reply to
bitrex
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Your question's over my head. That said, perhaps an actual test circuit can provide the answer you seek.

Recent threads piqued my interest in a CD4060B LTSpice model. A LTSpice CD4060B test circuit zip file is available for download at:

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That test circuit simulation may also come in handy for another relatively recent thread about LTSpice computational times. The CD4060B test circuit runs a transient simulation for 500s, probably to illustrate the typical waveforms found in a ripple counter.

It takes minutes to complete on my ancient W2003 terminal server. It may take less than a minute on a hotter PC.

Thank you,

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Don Kuenz KB7RPU
Reply to
Don Kuenz

No. It is better to use an XSpice based simulator :-)

or...The "alternate" solver is the high accuracy one, so not necessary, as its slower.

-- Kevin Aylward

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- SuperSpice
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Reply to
Kevin Aylward

I built a shift register in LT Spice, with the standard digital parts. It didn't work unless I added explicit prop delay directives.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

In XSpice based Spice's you can make a state machine to do any digital logic, all in the oner.

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This means that large digital designs could run 1000s times faster than LTSpice.

I never that stuff myself though, and haven't had the motivating to build much in the way of libs.

-- Kevin Aylward

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- SuperSpice
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Reply to
Kevin Aylward

I rarely use digital elements in Spice, and then just a few. We do massive amounts of digital simulation, but it's in the form of FPGA test benches, using special expensive tools.

My shift register was a pseudo-random noise generator, which was followed by analog active filters and FFT. That's a case where you need digital and analog in the same tool.

I just recently tried to sim a PLL in LT Spice, but it didn't work. I didn't spend much time on it, so I'll try again when things calm down. Simple XOR phase detector, narrowband, should work, so I'm doing something stupid. Maybe I should just breadboard it. It might take days to find lock in Spice.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

What little I've dabbled in XSpice, it seems impossibly retarded: as soon as one signal becomes "undefined" (usually represented as VCC/2), the house of cards falls apart.

Is there an obvious fix for that, or what? I can think of some hacks (like adding ADC+DAC junctions after each culprit, setting the threshold to redefine the "undefined" level as desired), but I don't recall seeing anything in the official docs. (The docs never discuss anything, either...)

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
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Reply to
Tim Williams

The circuit I'm messing with is pretty simple, it's built from 4 sections of a CD4093 and a few transistors as switches; two sections acting as a debounced flip-flop on/off switch and the others set up to load switch power to the 4093 itself and the microprocessor, and "lock out" the on/off switch and boost converter driving the main load (pretty LED display) when the thing's LiPo charger is connected to USB power.

It's a mod to an existing off-the-shelf kit, so I don't have access to the uP firmware to do it in software.

I shouldn't have said "purely digital" as it's actually working in that "hairball logic" regime in between analog and digital. My main concern was if those settings have any effect on startup behavior - in this simple case my brain can tell me by inspection a hairball circuit will start up in a defined state, but for something more complicated I might not be able to say.

Reply to
bitrex

Frankly for anything more complicated these days I probably shouldn't be hairballing it out of glue logic and just buy something designed for the task, anyway.. :)

Reply to
bitrex

"Oner"? What's that?

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Rick C
Reply to
rickman

Bitrex, I can't answer. But can you tell me where you get digital models for LTspice? I should have 'spiced my last "hair ball" logic board, cause I changed something, got the sign wrong and then had to respin the pcb. (I do a digital hair ball about once a decade so it's not a big need.)

George H.

Reply to
George Herold

There are idealized logic elements in the standard parts library. As I noted, the flops seem to need added prop delay to work right.

Someone posted an HC logic library here. I don't know much about it.

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John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
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Reply to
John Larkin

I'm using the ones that are available on the LTSpice user's group on Yahoo.com, the CD4093 model in particular. They have seemed to behave pretty close to reality in my experience.

If you don't want to make an account specifically for that and need a particular series I can pull what they have available and dropbox it to ya.

Helmut used to post here back in the day but has not been seen for a while.

Reply to
bitrex

OK thanks, I had an account there at one time. I copied JL's file to my HD. I guess I can hit up the LTspice group if I need help getting it to run in the future.

George H.

Reply to
George Herold

"Oner"? What's that?

All in one go. All at once.

-- Kevin Aylward

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- SuperSpice
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Reply to
Kevin Aylward

What does your simulator do about delays? If there are multiple FSMs in multiple subcircuits how do you make all the outputs update after all the inputs have been read? That is a problem in logic simulation. VHDL solves it by using delta delays, delays which impose order without assigning time delays so no simulation time elapses. I'm not sure how Verilog deals with it, I've heard it can be a problem.

I suppose this can be useful, but I'm sure you've thought of the project management issues of requiring two code bases for the same logic design. One in the analog simulation and the other in the logic simulation. I've gone the other route at times and added analog logic to my VHDL simulations. Nothing complex, just Rs, Cs and Ls. Hmmm, did I just make a joke?

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Rick C
Reply to
rickman

Sequential logic always needs delays of some sort to work right. Otherwise the output of one FF can be updated before the input of a FF it is feeding is read on the same clock. Signals then flow as if the FF is a buffer.

VHDL deals with this by adding delta delays which impose ordering of events without burning simulation time. Or in spice I add very small delay times. It also helps viewing the logic transitions in the waveform window. LTspice is not a very good logic simulator. Best to have it working before you enter it. It's damn hard to see what is going on when logic signals are all on the same Y alignment.

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Rick C
Reply to
rickman

That group has a bazillion people in it and one guy is the real expert. Better to try to work it out elsewhere or research in the group. I only ask questions there if I am really stuck. Recently I was trying to get something to work after not having used LTspice in a while. I did some searching and found I had asked the same thing a few years back! lol

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Rick C
Reply to
rickman

Happens to me sometimes, I'm pushing 40, last thing I need is any more confirmation that I'm soon to be an Official Old

Reply to
bitrex

Right, most of the time I'd want to add big delays (100ns), and just make sure my logic was correct. (I hardly do any digital stuff and it's most likely dead easy from your point of view.)

I was testing my last circuit for "glitches" and clocks are so good these days, that I had to tune my function generator off by ~10-100 uHz (10^-6) to watch it sweep through the synchro-steps. ~1 Hz clock. We can measure time better than anything. (I'm not sure if that's true or not.)

George H.

Reply to
George Herold

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