Locking a PLL to multiple references

You know who has a similar problem, the U.S. Naval Observatory which mainta ins a master clock service providing input to the GPS system. They integra te dozens of clocks into a single master clock. That said, I'm not sure ho w they do it exactly. I know it involves a Kalman filter.

I think you are right in using three PLLs. Each of these will provide a fr equency output as well as an indicator that it is in lock. A fourth PLL wo uld use as many of these three as are valid, measuring the phase difference of each, then attempt to lock to the average of these signals after adjust ing for the measured phase offsets.

While in operation the phase offsets would need to be constantly measured o ver some period and the offset factors adjusted.

You refer to the input as "mains". Is this at 50/60 Hz? That would make i t possible to do the phase measurements and adjustments in software along w ith the PLLs actually.

How much precision and accuracy are you looking for?

Rick C.

This reminds me of the burning cubicle problem; with sinusoidal loads the neutral of a 3-phase Y system never has more current than any hot leg. But if the load is non-sinusoidal (like a lot of old PCs) you can melt the neutral wire because the harmonics don't cancel.

How about a peaky polyphase bridge rectifier and a bandpass, 3x or 6x the line frequency.

Something like that?

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

Three separate phase-locked loops is a bad idea. Three separate voltage con trolled oscillators to generate the matching phases might not be.

A single master oscillator running at 1002 times 50Hz would be the obvious one to phase lock. You could use it to generate three 50Hz references 120 d egrees apart, and use them to drive six phase detectors on the three incomi ng signals to get in-phase and quadrature outputs from which you could gene rate the phase offsets between the master clock and each source, which you could then sum, and use to generate the phase correction signal for the mas ter oscillator.

The in-phase and quadrature outputs could also be decoded to give you the a mplitudes of the three incoming signals, and you could weight each of the p hase offset signals in proportion to the amplitude of the corresponding inc oming signal.

That should do it.

The process of extracting three phase references from a 1002-fold faster ma ster reference could give you as much phase-shifting as you would be likely to need.

If you want finer resolution, run the master oscillator faster. Anything fa ster than 50MHz and you have to start getting careful with you digital hard ware, but it's a long step up from 50.1kHz to 50MHz.

As Rick points out, you aren't.

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Bill Sloman, Sydney

:-)

This might be a good idea, thanks!

My other idea is as follows: since the actual phase combination is unknown, but there is only a limited number of them, maybe I should track all of them and select the one that fits best? At 50kHz the FPGA would mostly idle anyway...

Yes.

This is going to be implemented on an FPGA. My voltage data streams are

1.5 megasamples per second each an SW wouldn't handle that. I plan to decimate the phase detector outputs, but not the actual PLL block. 1/1000th of a period or sub-period, these two options are equally likely now.

Best regards, Piotr

a frequency output as well as an indicator that it is in lock. A fourth PL L would use as many of these three as are valid, measuring the phase differ ence of each, then attempt to lock to the average of these signals after ad justing for the measured phase offsets.

The reason why the USNO uses so many inputs to the master clock service is because even if one is not as accurate as the others, it still provides inf ormation and including it improves the overall result.

A friend did some contracting with them and asked me to get him started on HDL for the project. He told me a lot about what they were doing and it is pretty amazing.

s in software along with the PLLs actually.

What could you do with 144 processors running at about 700 MIPS each? Do y ou think that might handle this in software?

The chip even has five ADCs, lol. They have a variable resolution based on speed, so they might not have enough resolution at 1.5 MSPS. Looks like y ou can get about 10 bits at that rate.

This is a very odd duck chip. It's almost more like an FPGA than a CPU. T he processing nodes only have 128 words of memory which is both data and in struction. Each word is 18 bits which can have up to four instructions. T he processors are stack oriented with a simple instruction set. Inter-proc essor communications is word wide with hand shaking.

Some people think programming an FPGA is tricky. This thing is mind-expand ing!

Rick C.

Do you mean the Green Arrays Forth chip? Yes, I think it would do the job, but I prefer the more conservative approach if an FPGA can be considered as such.

I stick to the LTC1407 simultaneous sampling ICs. They have to be on the multiple hot sides, so no built-in ADC would help here. Using the same data the FPGA will also implement synchronous totem-pole bridgeless PFC, synchronous LLC, bi-directional high-current buck-boost, etc.

But this is for the future. My IO interfaces and safety circuits are mostly operational, so now it's time for a proper sync/timing unit.

I like the real-time capabilities of programmable logic and delegate to the software only as critical functionality as running a web server or blinking an LED.

My mind was expanded enough by programming a six-way registerless VLIW DFB block in its assembly language without a proper simulator. VHDL is predictable.

Best regards, Piotr

if the input phases are constrained to 3 values, i think you can frequency multiply each input by 3x. Then the 3x outputs will always be in phase with each other, phase lock to that. m

Take it a step further, multiply them by 1,000 or 1,000,000 depending on what accuracy you need.

NT

Could you square up your signals, filter out the third harmonics, sum them and use that to drive your PLL?

Cheers

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Clive

This is simply ingenious. Multiplication by 12 will also handle the

+/-90 and 180 degrees case. I think it is the solution I was looking for. Thank you, Mark!

Best regards, Piotr

This is equivalent to Mark's solution, but a digital PLL is far simpler than a digital bandpass filter. Cascaded PLLs are the winner now.

Best regards, Piotr

Or, you could make one PLL, and divide it down to make three 120-degree phase references, and from them generate three error signals (XOR type detector). The XOR outputs, 'if a phase drops out' case can be made to be a white-noise signal. That would be followed by summing the error signals (noise immunity of XOR phase comparators is a big advantage here) and feed that to the VCO.

I wasn't thinking digital for the third harmonic extraction, but a Goertzel algorithm should be easy.

Cheers

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Clive

your welcome

I got the idea from QPSK demods. They recover the carrier by x4.

Tried it in the lab. Took a QPSK signal looked at the 4th harmonic. Strong tone at the carrier. m

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quency multiply each input by 3x. Then the 3x outputs will always be in ph ase with each other, phase lock to that.

This isn't the problem here. Piotr is looking at mains frequency signals wh ich have a large component at 50/60Hz and relatively little higher harmonic content, which isn't true of quadrature phase shift keyed data signals.

His only problem is keeping track of the phases of his three components (wh ich aren't the same) and using them as a collective source to keep track of the changing phase of the remote master oscillator (at some remote place i n the power-generation system) which manifests itself in the same phase shi fts in each of the three examples he can see (and track).

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Bill Sloman, Sydney