line trigger

Den onsdag den 27. juli 2016 kl. 02.28.43 UTC+2 skrev John Larkin:

I've seen a variation used for all kinds of hall and VR sensors in a car ECU also with capacitor coupled inputs

one section of a HC14 is used to make an RC oscillator, the output is lowpass filtered and via resistors used to bias the other sections right in the center of the schmitt window

-Lasse

If I added a high value feedback resistor from the schmitt output to its input, it would self-center. It would also oscillate slowly with no input.

Banging the ESD diodes self-centers between the power rails, but is unaware of the schmitt threshold.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

Since threshold is generally Vdd/2, filtered *output* of the bias oscillator will usually *not* center the zero-crossing inverter's threshold.

Use the filtered *input* of the bias oscillator to bias the zero-cross detector instead, and you'll be fine.

C1 |\ a.c. >-||-+---| >O----> zero cross | |/ | [R1] .--[R2]--. | | |\ | '--+--| >O--' | |/ --- --- Cosc | ===

Cheers, James Arthur

Den onsdag den 27. juli 2016 kl. 06.03.50 UTC+2 skrev snipped-for-privacy@yahoo.com:

s

r ECU

owpass filtered and via resistors used to bias the other sections right in the center of the schmitt window

if the threshold isn't Vdd/2 it won't be 50/50 dutycycle

that'll probably make the output toggle at osc rate

Version 4 SHEET 1 972 680 WIRE 32 64 0 64 WIRE 160 64 112 64 WIRE 176 64 160 64 WIRE 304 64 256 64 WIRE 432 64 304 64 WIRE 0 176 0 64 WIRE 64 176 0 176 WIRE 160 192 160 64 WIRE 160 192 128 192 FLAG 0 240 0 FLAG 64 208 0 FLAG 304 128 0 FLAG 432 64 bias SYMBOL Digital\\schmitt 64 112 R0 WINDOW 3 53 104 Left 2 SYMATTR InstName A1 SYMATTR Value vhigh=5,td=10n,vt=1.2,vh=.3 SYMBOL cap -16 176 R0 WINDOW 0 -39 5 Left 2 WINDOW 3 -55 42 Left 2 SYMATTR InstName C1 SYMATTR Value 100n SYMBOL res 128 48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res 272 48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL cap 288 64 R0 SYMATTR InstName C2

TEXT 12 -40 Left 2 !.tran 100m

I think you are smoking some dope. The circuit you draw above *is* using the filtered output for biasing. It is also the input, that's how the bias circuit works.

--

Rick C

I do not smoke dope, but you're right, I screwed up.

Cheers, James Arthur

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car ECU

lowpass filtered and via resistors used to bias the other sections right i n the center of the schmitt window

Right, that's what I was (misguidedly) trying to fix, thinking "John needs

50/50 output from a sinewave input."

Ages ago I designed perhaps the first consumer spread spectrum transmitter and receiver. A key element was a 7x CMOS gate VHF frequency multiplier stage that depended on accurate 50% duty cycle, and I spent a lot of time achieving it.

That's what's bugging me here--I *remember* there's a subtle threshold problem that prevents a fed-back inverter from hitting

50/50 duty, but I goofed--John doesn't care about bias oscillator's duty cycle, and, as Rick so graciously pointed out, my 'fix' uses the averaged output anyhow, despite me trying not to.

Getting accurate 50/50 VHF from jellybean CMOS was vital to the

7x multiplier, but irrelevant here.

No, of course not. R1C1 >> R2Cosc.

You're pretty hard on that output! Why not use 50k instead of 1k in series and save energy? Global warming and all, you know.

Cheers, James Arthur

[...]

Scratching my head a bit, here's what bugs me. The net effect of the ESD diodes and RC filter is a d.c. level-shift of Vdd/2 across the coupling cap. That centers the gate input around Vdd/2.

That's fine if Vth(CMOS) = Vdd/2, but otherwise (e.g., 74HC14) the gate output edges won't accurately match the input zero crossings. And, timing will then also be somewhat Vin amplitude-dependent.

I think the diode-clamp d.c. restore overwhelms Lasse & my bias schemes.

I did an all-nighter yesterday, so I'm too punchy to fix it right now. But then again, you might not need accurate zero-crossings.

Cheers, James Arthur

Yup. It makes a nice squarish wave at the input of the gate.

I just need a 60 Hz trigger. It needs some lowpass filtering to remove glitches, and should be reasonably amplitude insensitive.

I just thought that driving a gate input through a capacitor was sort of fun. It seems to work.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

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Using a gate for a trigger like that will add jitter unless you have a real ly LOOOOOOOOOOOOOOOOOOOONG filter time constant, so it's an unwise approach . Break down and use a comparator, preferably one with an internal referenc e, a power supply derived reference would be junk too- something like a vol tage divider- no good.

[using a CMOS Schmitt gate]

It'd be nice if you could trust both the duty cycle and the phase, and have noise rejection. That's PLL talk, but sometimes it might be worth the overhead, and a '4046 is your jellybean.

50/50 duty cycle is relatively easy: this, for instance, does fine (note C2 is a kind of load component, the rest is self-explanatory)

• C:\Program Files (x86)\LTC\LTspiceIV\ACsenseComboInnominata.asc V1 N003 0 SINE(0 6 60) Q1 N002 0 N001 0 2N3906 Q3 N002 0 N001 0 2N3904 C1 N001 N003 100n C2 N002 0 50n .model NPN NPN .model PNP PNP .lib C:\Program Files (x86)\LTC\LTspiceIV\lib\cmp\standard.bjt .tran 0 0.2 0.1 .backanno .end

The AC line is pretty noisy already, and nothing short of a PLL is going to really clean it up. The input to the schmitt is practically a square wave if the AC input is say 5 volts RMS, so the schmitt thresholds don't matter too much.

Sometimes my customers want to line trigger our pulse generators, because their physics has some hum. I think SLAC was line triggered because the magnet power supplies had a bunch of hum, and mag fields were scattering the beam too.

As far as a comparator goes, the best reference voltage would be a nice stable ground.

--

John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

It *is* fun and there's nothing wrong with it.

A modified clamp gets its output transitions closer to the actual zero crossings (just riffing, I know you don't need it). This clamp centers the gate's d.c. input between its two thresholds, Vth+ and Vth-:

Vdd -+- | |/ .--| Q1 | |>. C1 |\ | | Vin >--||--+--| >O--[R1]--+---+ +---. | |/ | | | | | C2 --- | |

If I unraveled that correctly,

.-------. | | | | Vout | | |/ | .--| Q1 | | |>. | === | | | |/ >---||--+---| Q2 C1 |>. | ===

It would work as a cheesy line-trigger's zero-cross detector, too.

Cheers, James Arthur

... and other stuff

It'd work, of course, but gives two pulses per cycle; that confuses the phase info (if your SSR uses two SCRs, you wouldn't know which to fire).

PLL with a twisted-tail two bit counter can be tapped for pulse at 0, 90, 180, 270 degrees, trivially.

Or you can pick off the level of the input with a simple circuit as an enable/disable to generate two pulses.

--

Rick C