I am dealing with an IC house that is designing an ASIC with a LDO included. The input voltage is 9Vdc with 0.5Vpp ripple at 700KHz and 9.0Vout at 30mA. The output current has 30mApp of ripple current. They have an internal 2.5R P FET. It would be nice to have at least 30DB rejection. What magic is needed to control the P-gate?
Thanks, Harry