LDO Noise rejection

I am dealing with an IC house that is designing an ASIC with a LDO included. The input voltage is 9Vdc with 0.5Vpp ripple at 700KHz and 9.0Vout at 30mA. The output current has 30mApp of ripple current. They have an internal 2.5R P FET. It would be nice to have at least 30DB rejection. What magic is needed to control the P-gate?

Thanks, Harry

Reply to
Harry D
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With those specs, you need a battery--zero volts dropout with half a volt of ripple. You could jiggle the cold end of a big capacitor with a beefy op amp to keep the hot end still, but you obviously can't do that on-chip.

If you have a bit more dropout available, a sufficiently fast feedback loop could work. Myself, I like cap multipliers, but that won't help with the ripple in the load current, at least not with 2.5 ohms Ron.

Cheers

Phil Hobbs

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Reply to
Phil Hobbs

9V in and 9V out makes the pfet a short circuit. The gate can't do much under those circumstances.
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John Larkin         Highland Technology, Inc 
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John Larkin

On Sat, 04 Oct 2014 13:22:07 -0400, Phil Hobbs Gave us:

Absolutely must clean up the supply rail. Even POL modules are way better than that, and this thing can't be pulling too much power.

Simply mounting a nice, clean, off the shelf POL module next to the circuit would be a start.

Reply to
DecadentLinuxUserNumeroUno

9V in and 9V out makes the pfet a short circuit. The gate can't do much under those circumstances.
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John Larkin         Highland Technology, Inc 
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Reply to
Harry D

4V is a HUGE drop. Sounds like an extraordinarily bad design. Are they perhaps regulating via PWM rather than analog... to avoid the 120mW of dissipation?

Hire a pro >:-} ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Jim Thompson

4V is a HUGE drop. Sounds like an extraordinarily bad design. Are they perhaps regulating via PWM rather than analog... to avoid the 120mW of dissipation?

Hire a pro >:-}

...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Reply to
Harry D

Oh. 5V out makes more sense.

700 KHz is tough.

I guess the config is

pfet in-----------s d--------- out g | | some feedback

so as the source wiggles and the gate is held sorta steady by the feedback thingie, the 700K blasts through. The feedback loop would need huge gain-bandwidth to keep the output quiet.

You could study some commercial LDO data sheets, to see what their PSRR is like.

Do you need LDO? Using the pfet as a follower might be quieter.

What you need is some passive filtering!

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John Larkin         Highland Technology, Inc 
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John Larkin

With 4V of headroom, use an NFET follower. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Jim Thompson

[snip]

(1) I don't know of any papers. LDO's are really tricky to make stable. I got into LDO designs just like I do everything else... claim expertise, then become expert... as I did initially by putting distributed LDO's on several Aeroflex (Colorado Springs) custom chips, ten years or so ago >:-}

(2) 9V input suggests you might be running on an ancient, long-channel process... thus you be screwed.

(3) Use a reader that chops at --, you're making it difficult to reply-to. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Reply to
Jim Thompson

Why not use a depletion mode N-channel?

Two NPN transistors or a Darlington could also be used as capacitor multipliers. Maybe before the real regulator, to scrub those 700kHz. In a Darlington setting the capacitance can be quite small. I'd hang that on a pin of the IC as an external part to save real estate on the die.

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Joerg

May or may not be available in the process.

Harry D said this was an ASIC design... it may only have CMOS available in the process. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Reply to
Jim Thompson

A npn emitter follower is easier to stabilize (4v drop so you don't need a LDO)

Cheers

Klaus

Reply to
Klaus Kragelund

With 4V of headroom, use an NFET follower.

...Jim Thompson

I have the normal 0V to 4V of headroom with no real estate to add extra filtering. All must be done on board the ASIC. The grounds are somewhat non important so I might force them to use a N_FET on the return side. No noise and less drop but that will cause an rebellion.

Cheers, Harry

Reply to
Harry D

Pay attention to the details, Harry D said, "I am dealing with an IC house that is designing an ASIC..."

Unless it's a BiCMOS process any NPN's will be parasitic and crap-performance. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Reply to
Jim Thompson

At ZERO drop your rejection will be crap no matter the implementation.

A general rule of thumb is to operate in the saturation region:

0
Reply to
Jim Thompson

I meant nfet follower, of course.

Or NPN!

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John Larkin         Highland Technology, Inc 
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John Larkin

Not likely to be available on the ASIC process. From time-to-time I try to convince my customers that one external BJT can do wonders for their performance AND reduce their chip size... but their marketing dodo's insists on everything on the one chip :-( ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Reply to
Jim Thompson

Too bad. An NPN good for 30 mA could have really low capacitances.

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John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
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John Larkin

On-chip it can be huge, taking up a large percentage of the die area. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Reply to
Jim Thompson

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