What, no 1.25V versions of the ubiquitous TL431? Choose between LMV431, TLV431, ZTLV431, in sot-23 package; in this case save three parts! Featured heavily in AoE III, and Table 9.7. Reminder for new readers, free copy,
John, there's an ugly 200mV 50us overshoot at startup. But you can eliminate that with a 10n cap across R4.
--
Thanks,
- Win
Hey, John, try this setting to see the oscillations: .tran 0 500m 10m 10u uic
No, it's still a potential problem because of its high transconductance, lead inductances,** and the ceramic load cap. Gate resistor may not help, but adding a little source resistance would help, say 0.33 ohms for a 100mV drop at 300mA. You have a resistor now after the cap, move the cap to the right, increase its value. ** not in the sim.
--
Thanks,
- Win
As posted the circuit is fine just the gain is too high, reduce R5 (my guess is 10k?) and it should be OK.
piglet
Still overshoots at turnon. Added 1nF fixes.
--
Thanks,
- Win
Very true. Could be that the final application has the 1.8V rail sequenced to rise after 5V is stable. But extra ref decoupling still a good idea.
piglet
If you let LT Spice pick the time step, it doesn't oscillate!
-- John Larkin Highland Technology, Inc lunatic fringe electronics
We do have some LM4041-adj parts. Sort of similar. I prefer the opamp version, partly because my parts are on the BOM already. We are trying to pick-and-place the board with a single feeder setup, which is yet another complicating design constraint.
The power supplies soft-start, and a 200 mV overshoot wouldn't damage anything anyhow. I have 13 distinct power rails on this board so far (23 by another way of counting) and sequencing is getting interesting.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
I have a small forest of power supply tree. Looks like the lower voltage switchers (3.3, 1.8, 1.0) should be powered by the 5 volt switcher, so +5 comes up first. Switching 24 to 1.8 or 24 to 1.0 looks dangerous; duty cycles will be a few percent and on times around 100 ns.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
The 1mohm resistor is just there to plot the load current step; it's not real.
My experience is that adding source impedance makes a mosfet fet more likely to RF oscillate, but adding a gate resistor always kills oscillation.
I once theorized that the open-loop output impedance of an opamp would act like a gate resistor and stop oscillation. That turned out to be not so.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
I used the original LTSpice file you showed in ascii form, and didn't change anything, and it oscilates
Why would your simulation not do that? It cannot be a machine thing, it's really apparent (several hundreds of millivolts on the gate of the MOSFET)
Cheers
Klaus
Could be one of the many global settings. It's easily fixed, anyhow.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
That ought to raise a red flag in your mind.
Always set Solver = Alternate to avoid missed oscillations. Otherwise LTspice runs faster than any other simulator, conveniently skipping over embarrassing anomalies. ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| STV, Queen Creek, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I'm looking for work... see my website.
I have no idea what a DDR3 RAM is but looks like there're lots of high effi ciency very compact minimal component count microminiaturized switching sol utions, so who in there right mind would use a bunch of parts to make an an alog regulator? Is this 1.5V some kind of termination bias? Analog buys you nothing here.
I'm already switching 24 down to 1.8 (for the FPGA aux supply) so this is a sensible way to make 1.5. The "bunch of parts" is a pretty small bunch.
DDR3 is a category of fast (double data rate, which means using both clock edges to move data) dynamic RAM. I think most computers use DDR3 (or DDR4?) ram nowadays.
The dram controller in the FPGA actually experimentally calibrates and compensates for the delay of all the data lines. Timing is tight.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Yup. The Bode plot stuff is just what practitioners use to actually get stuff done (snarkity snark).
I feel that control theory has moved away from what ordinary people can grasp intuitively -- this is a shame.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!
A (real) rocket scientist I know says that the Space-X "lands itself" rocket has a control loop that was cooked up entirely by running simulation after simulation, without anyone ever sitting down and doing the pencil-and-paper work.
Watch it land and it looks it -- particularly when it's blowing up.
-- Tim Wescott Wescott Design Services http://www.wescottdesign.com I'm looking for work -- see my website!
It's like economics and psychology: the first two freshman semisters make a lot of sense, and it goes downhill from there. By the time someone has a PhD in economics, they are useless... at best.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
:
to
fficiency very compact minimal component count microminiaturized switching solutions, so who in there right mind would use a bunch of parts to make an analog regulator? Is this 1.5V some kind of termination bias? Analog buys you nothing here.
Okay, thanks for the explanation. You have a ton of parts and headache comp ared to something like this
The same goes for Pspice. You need to actively think about the circuit and the maximum time step you can defend, otherwise fast transients and oscillations may be overlooked
Cheers
Klaus
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.