Hi, I am building a cascode current source which is derived from a self biased JFET current source. I do not get how these are biased. If J1 is in constant current region how will J2 is biased. Please help me understand this. . | |-+ | J1 o------>|-+ | | | |-+ | | J2 .------>|-+ | | | | | | .-. | | |R1 | | | | '-' | | '---------' (created by AACircuit v1.28.6 beta 04/19/05
This requires that J1 have a higher Vgs at the operating Id than J2 has. J2 operates with its Vds equal to the Vgs difference. Because this Vds voltage changes very little with Vd on J1, the circuit exhibits a lower Id change with Vd.
Winfield Hill snipped-for-privacy@rowland.org posted to sci.electronics.design:
Win, please do not do these twits homework for them.
Sorry, but I see that his answer will be marked wrong, because I left out a critical piece.
Thanks a ton Win, By the way, i think i have passed the age of getting homeworks long ago:). I found an old scope and am tearing it apart (being a biologist i like the term "tearing apart") to look at some of the circuits.
Boston University medical campus, eh?
Best regards, Spehro Pefhany
-- "it\'s the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.com
The missing piece of analysis is, of course, that Vgs1 must be greater than Vgs2 + Id R1. So you've found this circuit in an old Tek scope? I wonder what JFETs they used. IIRC, if they're special Tek numbers we may still be able to find equivalents, but it's likely they would be selected parts, for the desired Vgs voltage range.
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