Int-amp pulse response

Weird. I could see it if it were a two-amp design, but it's a normal three-amp one, which should be pretty symmetrical, and the datasheet indicates it has plenty of AC CMR in the millisecond range.

The second stage has an asymmetrical input impedance (40k inverting, 80k noninverting). It runs at fixed gain, though, so there should be no gain-dependent funnies there unless the open-loop output impedance of the first stage amps is really high, which could be. That would be my guess faute de mieux. (A schematic would help.)

Do you see the same behaviour on the trailing edge?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
https://hobbs-eo.com

I don't understand your results, nor do I understand your test. Are you grounding one side and applying a signal through 1G to the other side? Nah.

Anyway, one comment, if you hope to have good common-mode rejection, it's necessary to present equal impedances to both sides. Manufacturers do the test with low-Z in, and also with a 1k imbalance. Table 5.8, in AoE III, has a column showing if the spec is for the harder 1k imbalance. 1G imbalance, forget it.

BTW, I elected not to include the INA121 in the table, don't remember why. They avoid the 1k imbalance.

--
 Thanks, 
    - Win

Thanks for responding Phil, I'm not sure it's weird. I assume it has to do with stray capacitance, from output to input. (A tacked a wire onto the output and then hold it near the inputs, that can make it weird.) I was thinking I should try and spice it. How hard is it to use TI models in LTspice? Maybe easier to learn TI-spice?

Not much too it. BNC, switch, lnd150's, Int amp.

Hmm this is the pulse response.. chan. 1 is the pulse ~200mV and

100 us wide. The step response doesn't look nearly as different. (rising or falling)

In practice there will be more capacitance to ground on the inputs (cables and such) so things will be even slower. For testing I made a little box that plugs right into the front.

George H.

I don't see any inputs on that schematic. Where's the 1G resistor?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC / Hobbs ElectroOptics 
Optics, Electro-optics, Photonics, Analog Electronics 
Briarcliff Manor NY 10510 

http://electrooptical.net 
https://hobbs-eo.com

Yeah, Well actually I've got a chain of three R's. This is sorta my worst case sample/ signal.

Sig gen.--1G--+--1G--+--1G--gnd | | input input

I short one input and look at the output. Then flip it over and short the other side. I guess I'm trying to measure how well balanced each side is.

I looked with lower R's also.. 10 Meg, 1 Meg...

I'll look table 5.8... (Oh figure 5.82, CMRR vs freq is worth the price of the book IMHO)

I was looking for low bias current. The spec sheet does recommend using the INA116 for impedances greater than 1 Meg, I guess I ignored that recommendation. (Well purchased IC before a careful read of spec sheet. :^)

George H.

Right, sorry, The only parts on the schematic are those that go on the pcb.

BNC inputs go to the center pin of the switches. I've got a box with three R's that I can change. (See reply to Win...) I'll take a real pic outside

inside.. well a bit blurry sorry.

I think I'm just measuring my layout capacitance.

George H.

The spike is capacitive feedthrough to the amplifier, and the decay is the RC time constant back to where the signal belongs? Most of the action may be in your test box, and the rest on your PCB.

--
 Thanks, 
    - Win

Thanks Win, Right I made some screw up on the smd layout. I don't understand why it's worse. I'll have to post pics of the pcb.

George H.