Input Amplifier

I got help from Joerg some time back with an amplifier for an antenna signal for WWVB at 60 kHz. I was looking at a version in LTspice and noticed the bypass cap on the source leg of the second stage was a lot smaller than the others doing a similar job. It was reducing the gain of the second stage a bit and I increased it from 3.3 nF to 33 nF. Oddly enough, it dropped the gain of the first stage about the same amount it increased the gain of the second stage.

At first I thought it might be something to do with loading the first stage output with increased capacitance, but I can't see how that would be right. So I'm thinking it has more to do with just the loading of the first stage by a different input impedance on the second stage, but I can't convince myself of this either, it's a JFET, not a bipolar transistor.

So what is going on?

Here's the schematic I'm simulating...

Version 4 SHEET 1 1940 680 WIRE 1008 -384 1008 -416 WIRE 816 -288 816 -336 WIRE 1008 -256 1008 -304 WIRE 1136 -256 1008 -256 WIRE 1440 -256 1136 -256 WIRE 1008 -224 1008 -256 WIRE 1440 -224 1440 -256 WIRE 816 -160 816 -208 WIRE 816 -160 704 -160 WIRE 896 -160 816 -160 WIRE 960 -160 896 -160 WIRE -48 -144 -96 -144 WIRE 48 -144 -48 -144 WIRE 48 -128 48 -144 WIRE 368 -128 368 -160 WIRE 816 -128 816 -160 WIRE 1440 -128 1440 -160 WIRE -96 -112 -96 -144 WIRE 704 -112 704 -160 WIRE 1008 -32 1008 -128 WIRE -96 -16 -96 -32 WIRE 48 -16 48 -64 WIRE 704 -16 704 -48 WIRE 816 -16 816 -48 WIRE 816 -16 704 -16 WIRE 368 0 368 -48 WIRE 416 0 368 0 WIRE 480 0 416 0 WIRE 640 0 544 0 WIRE 816 16 816 -16 WIRE 368 32 368 0 WIRE 1008 32 1008 -32 WIRE 240 96 -16 96 WIRE 320 96 240 96 WIRE 640 96 640 0 WIRE 832 96 640 96 WIRE 960 96 832 96 WIRE 240 144 240 96 WIRE 368 144 368 128 WIRE 448 144 368 144 WIRE 496 144 448 144 WIRE 1008 144 1008 128 WIRE 1088 144 1008 144 WIRE 1136 144 1088 144 WIRE -16 160 -16 96 WIRE 368 176 368 144 WIRE 640 176 640 96 WIRE 1008 176 1008 144 WIRE 496 192 496 144 WIRE 1136 192 1136 144 WIRE 240 256 240 224 WIRE -16 288 -16 240 WIRE 368 288 368 256 WIRE 496 288 496 256 WIRE 496 288 368 288 WIRE 1008 288 1008 256 WIRE 1136 288 1136 256 WIRE 1136 288 1008 288 WIRE 368 336 368 288 WIRE 640 336 640 256 WIRE 1008 336 1008 288 FLAG 368 336 0 FLAG -96 -16 0 FLAG -48 -144 V2.2 FLAG -16 96 Vin FLAG 240 256 0 FLAG -16 288 0 FLAG 48 -16 0 FLAG 368 -160 V2.2 FLAG 448 144 Vs FLAG 1008 336 0 FLAG 1136 -256 Vout FLAG 1008 -416 V2.2 FLAG 1088 144 Vs2 FLAG 640 336 0 FLAG 416 0 Vd1 FLAG 832 96 Vin3 FLAG 1440 -128 0 FLAG 816 -336 V2.2 FLAG 896 -160 Vb FLAG 816 16 0 FLAG 1008 -32 Drain SYMBOL voltage -96 -128 R0 WINDOW 123 0 0 Left 2 WINDOW 39 24 124 Left 2 SYMATTR SpiceLine Rser=1 SYMATTR InstName V1 SYMATTR Value 2.2v SYMBOL voltage -16 144 R0 WINDOW 123 24 152 Left 2 WINDOW 39 24 124 Left 2 SYMATTR Value2 AC 1 SYMATTR SpiceLine Rser=0.00001 SYMATTR InstName V2 SYMATTR Value SINE(0 5uV 60K) SYMBOL res 224 128 R0 SYMATTR InstName R1 SYMATTR Value 10Meg SYMBOL cap 32 -128 R0 SYMATTR InstName C5

SYMATTR SpiceLine Rser=0.1 SYMBOL res 352 -144 R0 SYMATTR InstName R3 SYMATTR Value 270k SYMBOL njf 320 32 R0 SYMATTR InstName T1 SYMATTR Value JBF862 SYMBOL res 352 160 R0 SYMATTR InstName R2 SYMATTR Value 150k SYMBOL cap 480 192 R0 SYMATTR InstName C1 SYMATTR Value 33nF SYMBOL res 992 -400 R0 SYMATTR InstName R6 SYMATTR Value 220k SYMBOL njf 960 32 R0 SYMATTR InstName T2 SYMATTR Value JBF862 SYMBOL res 992 160 R0 SYMATTR InstName R5 SYMATTR Value 150k SYMBOL cap 1120 192 R0 SYMATTR InstName C3 SYMATTR Value 3.3nF SYMBOL cap 480 16 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C2 SYMATTR Value 33nF SYMBOL res 624 160 R0 SYMATTR InstName R4 SYMATTR Value 1Meg SYMBOL cap 1424 -224 R0 SYMATTR InstName C4 SYMATTR Value 10pF SYMBOL cap 688 -112 R0 SYMATTR InstName C6 SYMATTR Value 33nF SYMBOL res 800 -144 R0 SYMATTR InstName R7 SYMATTR Value {R7} SYMBOL njf 960 -224 R0 SYMATTR InstName T3 SYMATTR Value JBF862 SYMBOL res 800 -304 R0 SYMATTR InstName R8 SYMATTR Value 3.3Meg TEXT 240 -312 Left 2 !.ac dec 10 100 10Meg TEXT -24 400 Left 2 !.lib spice_BF862.prm TEXT 240 -344 Left 2 ;.step param R7 500k 1.3Meg 0.1Meg TEXT 240 -376 Left 2 !.param R7=680K TEXT 240 -408 Left 2 !.options plotwinsize=0

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Rick
Reply to
rickman
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Don't know... is R7 missing a value?

George H. (At 60 kHz, why not a nice opamp?)

Reply to
George Herold

Defined by a parameter or a step value. I was playing with the biasing. Still not sure how close to the fire I can get with that one. I can boost the gain a bit but I reduce the range of the output. Not sure it matters unless I get strong interference on the input. The signal will be well below the noise level and will be dug out of the dirt by DSP since it is very narrow bandwidth.

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Rick
Reply to
rickman

I doesn't here. I assume you mean C3 in your schematic. When I change that to 0.033u it doesn't have much of an impact at 60KHz.

It does change the input capacitance of T2 but only a wee smidgen, not enough to write home about.

If you make those caps too large you extend the high gain region to lower frequencies. In this day and age that can spell trouble because of all the switchers, ballasts, Chinese LED lamps and so on. It can choke whatever input gets hit with the output singal.

[LT Spice schematic in original post]
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Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

I don't see a big change. The gain at Vin3 drops 2 dB and the overall gain at the output barely changes at all. It just struck me odd that C3 would have an impact on the signal on the gate of T2 since there is virtually no input current and the output impedance of T1 isn't that high.

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Rick
Reply to
rickman

You may be running out of voltage in the output cascode stage.

2.2V is pretty little, accounting for the required biases on both JFETs.
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-TV
Reply to
Tauno Voipio

Without actually running the simulation and wildly waving my hands, I'd guess it's the Miller effect around T2. It's cascoded, I know, but the impedance into T3's source isn't all that low, the way you've biased things.

You can check the input impedance of the 2nd stage by plotting V(VIN3)/I(C2).

Jeroen Belleman

Reply to
Jeroen Belleman

Probe the input current, it changes by about 2dB as well :-)

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Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

Why a casc_o_de at only 60kHz?

They really come into their own at high frequency (VHF/UHF etc) but have pretty high output impedance.

They're favourite in HD video outputs, but require complementary emitter follower pairs to drive CRT cathode capacitance.

Reply to
Ian Field

They also come into play when, like in this case, Rick is trying to get away with the least amount of supply current possible. That is where every picofarad and Miller and all that already starts to matter at low frequencies.

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Regards, Joerg 

http://www.analogconsultants.com/
Reply to
Joerg

That is what confuses me. At 60 kHz the impedance of C3 is some times larger than R5. The capacitance of the gate to source is small so the impedance is much larger than the source biasing network. So the overall effect of the change in value of C3 should be minimal. I see less than a -1 dB change in I(g). I don't understand the cause.

Does this have to do with the gain of T2? With no bypass cap, the impedance of R5 is amplified by the gain to appear at the gate, no? The addition of capacitor C3 reduces this impedance. Increasing the value of C3 further reduces the impedance. This gain multiplied impedance is added to the impedance of the gate to source capacitance which must be much larger than the biasing network, no? Am I screwing this all up?

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Rick
Reply to
rickman

The question is about the loss of gain in the first stage. Increasing the value of C3 improves the gain of the cascode stage. The signal is very small, so only a little bit of head room is needed I think. I'll be happy if the output can be a few milivolts.

The first stage gain is reduced by increasing C3. That is the part I fail to understand.

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Rick
Reply to
rickman

I used an old Motorola TV IF amp IC in my WWVB antenna, the MC1430, which is now obsolete. The antenna was powered via the coax, and I had over eight volts of 60 KHz signal at the power inserter's RF output. The fun part was winding 50 turns inside a 3' square copper frame made of 3/4" copper pipe with square corners. :)

Reply to
Michael A. Terrell

As the cap goes up 10 fold, the input voltage Vin3 and the second stage input impedance go down by 2 dB. I get that as the input impedance changes, the voltage will change because of the output impedance of the first stage. But I don't get why the input impedance changes so much. I have it in my mind that the input impedance is dominated by the gate to source impedance.

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Rick
Reply to
rickman

Yeah, winding wire in tubing is a lot of work. Some manage that by using ribbon cable and soldering the wires with an offset of one to form a 50 turn loop. I'm using RG-6 coax. But the calculations indicate the output voltage will be *very* small, *maybe* a micro-volt if I can keep the Q up and use a multi-turn transformer for the coupling.

I'm trying to keep the power consumption very low, so I've not found any amp chips that will do the job without drawing lots of current.

Did you use the preamp on the antenna? Sounds like it with a power inserter.

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Rick
Reply to
rickman

In message , rickman writes

You're running the FETs at too low a current; the gm is non existent . Drop the source and drain resistors by a factor of 10.

If I do that I get 66dB gain at 60kHz

Brian

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Brian Howie
Reply to
Brian Howie

Have you played around with changing the supply voltage? That might tell you something.

George H.

Reply to
George Herold

(I just replaced them with the standard jfet.. ) GH

Reply to
George Herold

Nobody else had trouble with the JBF862 model instance?

RL

Reply to
legg

Which one?

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-TV
Reply to
Tauno Voipio

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