I'm popping MOSFETS....linear derating factor involved?

In parallel? If so, then what method are you using to force current sharing?

RL

There are no good phase-change compounds. Use thermal silicone grease.

That's pretty good with grease, although 18 lbs is a little wimpy maybe.

I'd be suspicious of a fet rated for 470 watts. We tested a pile of different fets rated 300 watts and up and only found two that could honestly dissipate 300 watts for 100 milliseconds bolted to a copper block. The rest turned into shrapnel.

Plus, even with a half-inch baseplate, thermal spreading resistance will be a killer. The best thing for you to do might be to go with more fets, and add some discrete power resistors in the drains to share the dissipation if your application permits.

John

Each MOSFET is individually controlled by it's own op-amp loop. The current level is stable.

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I'm finding that Aavid's Ultra-Stick compound is giving me better performance (lower thermal resistance) than any silicone grease I've used....about 0.022 degrees-C/W according to my tests.

I agree, I may go back to a standard TO-247 case (instead of Super TO-247 without the screw hole) screw mounting with belleville washers. There is a better clip (Aavid's MAX08, 27 lbs. for a TO-247 case) but I haven't found it available anywhere.

Each FET only dissipates 125W, which I thought would be readily achievable. Especially with the case and heat sink temperatures I'm reading. It's that darn derating factor I'm worried about. :-)

I did have twice the number of FETs in my original prototype (spread around the heat sink) but the extra wattage I could dissipate didn't seem worth the extra op-amp control loops I'd need to hook up. But, I may have to do this if the derating factor is "causing" my problems.

Early on I had considered using higher-power drain resistors to help with the dissipating (way beyond the 3W ones I use for current sensing now). Might be worth considering again. :-)

Thanks!

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Were you going to give us any part numbers, and circuit details?

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 Thanks,
    - Win

If you're discharging batteries, why not use drain resistors as the real loads and PWM the fets? That would save a ton of money all around and be pretty much indestructable.

John

Well, originally, no. :-) With my testing to confirm that the circuit was stable and no other ratings were exceeded I was concentrating on the "other" stuff like derating factors. Especially since the circuit is based on one you gave me last year. But, here it is. I could be very wrong about my asssumptions that exceeding the total power rating for the FET could be my only problem.

. Vcc 5V . | . 1K . | . +------, +5V ,-----+----- LOAD+ . | | | LT1013 | | . 1.25V POT --+--R6-- G | . -+------+-, | | ,--|-/ | S | . | | | | | === C1 | | . | | | | | | | | . +--|--R3--|--+----|---+---R5----+ | . | | | | | | . | | | | R7 | . | | | | | | . | | '--R4---+-------------+-----|-+--- LOAD- . | | | | . | | | | . | | +5V ,-----+ | . | | | | | . | +--R2--+-----|+\\ D | . | | | >--+--R6-- G | . | | ,--|-/ | S | . | | | | === C1 | | . | | | | | | | . LOW-LVL GND+-----R3--|--+----|---+---R5----+ | . | | | | . | | R7 | . | | | | . '--R4---+-------------+-------+ | HI-AMP GND

R2, R3 = 49.9K,1% R6 = 1K,1% R4, R5 = 10K,1% R7 are 0.01ohm,1%,3W C1 = 0.01uF monolithic ceramic MOSFETs are IRFP2907 or IRF1405.

LOW-LVL GND and HI-AMP GND are brought back separately to the supply's GND pin.

Prototype circuit is breadboarded with short leads, well decoupled with a quiet linear power supply. After setting the pot, current is steady to within 0.1A up to 30A (max for my tests). Scoping out the power supply, inv. and noninv. inputs to op-amps and gate lead to MOSFETs shows no more than 4-5mV of noise.

John

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Good idea, I think I'll do the math again. I think I remember that the current levels were too high to make that practical (over 100A at

0.9V min.) but it's worth revisiting.

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Are you sure nothing's oscillating?

John

I can't find anything more than 5mV of noise or voltage variation anywhere with the scope. I tried grounding the probe to both the main supply ground and at op-amp gnd (and measuring around). Even when that noise on the input to the op-amp, the cap on its output seems to slow everything down enough to not let the noise affect the MOSET's gate voltage.

My (possibly) exceeding the total dissipation rating of the FET isn't a possible cause for the popping of FETs too? Still don't know if my calculations and assumptions about linear derating factors are right.

John

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No. For each degree that the case rises above 25C, you can dissipate

3.1W less than 470W. That's what the derating means.

So you need to know how many degrees the FET case rises above ambient for a given dissipation. Usually you will have to measure that rather than calculate it because it depends on how large the heatsink is and how good the airflow is.

When it's operating at the normal load that does *not* blow up the FET, leave it like that for half an hour or whatever it takes to reach equilibrium temperature. Then measure the FET case temperature with a temperature probe.

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Dave Farrance

It's not the temperature rise of the junction that's used? I was calculating the temp rise in the junction (based on measured case temp) instead. I have the case temperature from earlier on, before the FET blew. Here goes...

Max power rating for FET = 470W Linear derating factor = 3.1W/degree-C Ambient temperature = 25C Measured case temperature = 100C (actually, it's 97C but I rounded up) Case temp rise = 100C - 25C = 75C Derating = (3.1W/degree-C) x (75C) = 232.5W Power available to FET as a load = 470W - 232.5W = 237.5W

This seems to indicate that the 125W load the FET was dissipating at a case temperature of 100C wasn't a problem (by itself). But, the junction temperature was a lot higher (140C, calculated). Shouldn't the temperature rise of the junction be the basis for the derating?

Thanks!

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The critical parameter in this sort of design is the junction temperature. You design to keep the junction below some maximum (125C on most ICs, I see 150 or 175C on some transistors). Any derating has to do with insuring that the junction temperature is less than the maximum allowable.

So, for instance, if you have a 175C maximum junction temperature, a

3.1W/K thermal resistance, and a case temperature of 174C, you'd better hold the dissipation to 3.1W!

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Wait...a case temp of 174C, or a junction temp of 174C limits me to

3.1W? I'm hoping it's the junction temperature as that would make sense.

I was thinking about all of this and realized that a great way to picture it (I beleive) is to not think about the power I'm dissipating but to only concentrate on the junction temperature at first. If my junction is at 140C (steady state temp, at the power level I want), then I need to get my derating calculated before I can even begin to consider how much power I can dissipate.

I would take that junction temp, subtract the ambient temp, multiply it by the derating factor, subtract that from the max rated power for the FET and arrive at a derated power rating for the MOSFETs/load/heat sink/grease/etc. I'm using:

(470W) - ((140C - 25C) x (3.1W/degree-C)) = 113.5W

Since I have the MOSFETs dissipating a 125W load (each) when at a junction temperature of 140C, I believe that means I'm in trouble. It could certainly explain why I'm popping FETs after a few minutes/hours.

And that's not even starting to address that 140C is just too darn high all by itself....100C is great, 125C is max IMHO (for a 175C rated device).

I have noticed that my case temperatures are averaging 14C higher using the Aavid MAX07 clips vs. screw mounting. Going back to screw-mounting the TO-247 cases, and bringing the junction temp back down to around 123C (earlier calculated value based on 83C case temp measurement), is definitely going to help. Just doing that brings my derated power rating up to:

(470W) - ((123C - 25C) x (3.1W/degree-C)) = 163.1W (I believe)

Not a great safety margin for a 125W load, but a heck of a lot better than before! It's amazing what a simple change in mounting can do. :-)

John

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No. A case temp of 174C with 3.1W/K thermal resistance means that you can only dissipate 3.1W before you hit a maximum Junction temperature of

17_5_ C. (obviously this is an absurd example -- if you really have to operate at 174C you know you're operating in no-man's land anyway).

What? You're confusing yourself (and me). All the derating stuff is there for people who don't understand thermal resistance (I'm opening myself up for comments here, I know it).

All you need to know is the maximum allowable junction temperature (either the manufacturer's or yours), the thermal resistance to ambient, and ambient. So if ambient is 25C (it never is) and your maximum allowed junction temperature is 175C then your allowed temperature rise is

T_rise = T_jmax - T_ambient = 150K (note the switch to Kelvin -- this is just a quirk on my part)

If you know that your thermal resistance from junction to ambient is

1K/W then this means that you can calculate the dissipation from

P_max = T_rise / (thermal resistance) = 150W

So you've calculated a junction temperature of 140C? I assume your devices are rated for 125C, or something less than 140C, then.

175C junction temperature is max for a 175C device. That's why they say that. You may wish to derate further, depending on how much you trust the manufacturer. _Package_ temperature is different, but you can work out the _Junction_ temperature from dissipation, package temperature and thermal resistance.

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Tim Wescott
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Posting from Google?  See http://cfaj.freeshell.org/google/

OK, this is good. Thermal resistance I know about. :-)

With the linear derating factor calculation results I got, I'm concerned that I might not have the proper thermal resistance data though. Calculating the junction temperature from the measured case temperature gives me this:

T_junction = (T_case) + (P_dissipated) x (Theta_junction-case) T_junction = (100C) + (125) x (0.32) T_junction = 140C

The device is rated for a 175C max junction temperature, so it appears we're OK (but little-to-no safety margin, that's OK for now), but I'm still blowing FETs. We're running the tests again to re-measure any possible noise/spike/oscillations but we're pretty sure we have a clean, stable test rig that isn't blowing up the FETs for us.

When the derating calculations are done though, it shows I have a problem. Derating P_max leaves me with a value of 113.5W. With a load of 125W, that could definitely explain why FETs are popping.

Seems that either the Theta_junction-case for the FET is not the same as that quoted in the datasheet or calculating junction temperature is often not as easy as using the one equation above...which I've heard and read about quite often. :-)

John

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Viewing the schematic, I can see no fault in the sharing method, however you should be wary driving these parts from a 5V source, as some may not be capable of the full intended load at this gate voltage, particularly if the source resistors have a signifigant voltage drop.

This would mean that those that can, will pass more current than their compatriots. Easy to check with a voltmeter.

I wouldn't trust clips as far as I could throw them, in a high current/power/temperature application.

RL

yep, thats it.

mostly manufacturers like to use wildly optimistic (read as: bullshit) figures for the power handling capability. they do things like assume Tj = 25C.

dont forget that your Tj is very sensitive to Rtheta, which is pretty low at 0.32K/W. It wouldnt take much to accidentally crank it up to say

1K/W, at which time Tj skyrockets to 220C. loose screw, too much goop, slightly warped heatsink etc.

IME devices need to be torqued down with appropriate hardware (eg belleville washers) to prevent loosening (clips can be great). I have done failure analyses on literally hundreds of dead converters, and found many to be due to inconsistent screw tightening.

in one funny case, the contract manufacturer used a nylock nut on the FET of a smps. The FET heated up to about 100C, the nylon in the nylok nut melted, the nut came loose and kablooey. when I opened up the unit, the nut weas tight on the bolt (with a blob of melted plastic hanging out of it) and the FET free-spun on the heatsink when desoldered.

As a result of these experiences, I get my techs to check the fasteners (tighten up with torque wrench) before repair, otherwise they destroy the evidence....and of course use torque control during manufacture.

Cheers Terry

Yes.

And Tc means case temperature (normally!). But I didn't stop to think that if you were assuming that it was junction temperature, then you should have been giving yourself an extra safety margin. Even more puzzling that you're blowing up FETS then.

Clutching at straws: how close are you to the current limit?

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Dave Farrance