For my day job I'm attempting to design a planar transformer for an LLC converter, which pushes up to 50W. The tricky part is that some of the secondary windings require 3.5kV of isolation between them.
This will go on a board which will be potted, and we use 100V/mil clearance and 20V/mil creepage as our design rules for everything once it's been potted.
However, I'm trying to figure out what spacing guideline I should use between traces on the same internal layer of the planar PCB. Specifically, the spacing between a through-hole via and a trace which need 3.5kV of separation.
Then google told me this:
- For FR4 you can assume 1000V/mil between separate layers, and 300V/mil if you want to derate heavily.
- IPC-2221: 300mil separation for 3.5kV in internal layers (around 12V/mil)
So why so low as 12V/mil, when the prepreg between the traces is also FR4? I figured it must be the creepage along the boundary of the prepreg. How pure is the insulator along the prepreg/core boundary??
Then google told me this:
- Industry standard is 1% voids (air pockets) by volume, for any prepreg material.
- The boundary between prepreg and core is hermetic, unless delamination occurs. Delamination can be caused by humidity or by overheating during soldering.
Assuming I can ensure the unit is potted without exposure to excessive humidity, and since the only thing soldered to this PCB are the pins, can I forget about the 12V/mil spacing? I would be happy to use 100V/mil.
I appreciate any wisdom you all might have on this topic.
P.S. The backup plan is to use a toroid wound with HV insulated wire, but I am looking to reduce the number of manufacturing steps and take advantage of the repeatable circuit values of a planar.