HV creepage requirements on internal layers of PCB (2023 Update)

For my day job I'm attempting to design a planar transformer for an LLC converter, which pushes up to 50W. The tricky part is that some of the secondary windings require 3.5kV of isolation between them.

This will go on a board which will be potted, and we use 100V/mil clearance and 20V/mil creepage as our design rules for everything once it's been potted.

However, I'm trying to figure out what spacing guideline I should use between traces on the same internal layer of the planar PCB. Specifically, the spacing between a through-hole via and a trace which need 3.5kV of separation.

Then google told me this:

  1. For FR4 you can assume 1000V/mil between separate layers, and 300V/mil if you want to derate heavily.

  1. IPC-2221: 300mil separation for 3.5kV in internal layers (around 12V/mil)

So why so low as 12V/mil, when the prepreg between the traces is also FR4? I figured it must be the creepage along the boundary of the prepreg. How pure is the insulator along the prepreg/core boundary??

Then google told me this:

  1. Industry standard is 1% voids (air pockets) by volume, for any prepreg material.
  2. The boundary between prepreg and core is hermetic, unless delamination occurs. Delamination can be caused by humidity or by overheating during soldering.

Assuming I can ensure the unit is potted without exposure to excessive humidity, and since the only thing soldered to this PCB are the pins, can I forget about the 12V/mil spacing? I would be happy to use 100V/mil.

I appreciate any wisdom you all might have on this topic.

P.S. The backup plan is to use a toroid wound with HV insulated wire, but I am looking to reduce the number of manufacturing steps and take advantage of the repeatable circuit values of a planar.

Reply to
sea moss
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What were the actual references for this info. Saying Google doesn't make that clear. I see where you cite IPC-2221, but what about the other info?

Rick C.

Reply to
gnuarm.deletethisbit

I was worried someone was going to ask that. I didn't save any of these references, let me see if I can find them again...

Reply to
sea moss

Don't sweat it. I'm just wondering how it could be as low as 12V/mil. I was thinking maybe it is much higher like 12kV/mil although that seems rather high. I thought there might be a typo on the web page.

Rick C.

Reply to
gnuarm.deletethisbit

Circuit board and potting both count as a "cemented joint" in IEC/UL

60950-1. YMMV for other standards, but I imagine most are similar.

IPC-2221 is deprecated; follow a current standard.

Obviously enough -- find which standards /are/ actually applicable to your product! Consult a compliance/test lab if you need help finding these (their expertise is well worth it).

There is no such thing as creepage under potting, as long as it is free of voids. You only need to use the direct, through-material dielectric breakdown figure. (Handy!)

Do take lengths to ensure good potting. Make sure the correct mixing and pouring methods are used. Use vacuum. Do not use a rigid compound, which can crack components off the board; rubbery formulations are best. Where high voltages reach components, ensure underfill by adding a hole or slot beneath the component.

It sounds like this will probably not apply anywhere in your circuit, except if you're using SMTs for Y-caps, and except for the planar transformer core, which would be difficult to ensure good underfill on. In that case, make sure the core doesn't see voltage, by putting the same circuit on the outer layers of the stackup, or using two extra layers so the outer layers can be bare, or shield layers.

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:

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Reply to
Tim Williams

Here's a copy of IPC-2221 online:

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on page 39 there's a formula for HV spacing on internal layers. for 3.5kV, the formula gives 305mil, which comes out to 11.5V/mil

Reply to
sea moss

Thanks for the input Tim. Glad to hear that IPC-2221 is outdated. I'll as k around about which compliance labs we use.

We do our potting in-house, and it is a rubbery material. I have been aski ng questions about our process but haven't seen it with my own eyes yet. W e do use vacuum.

I have kept in mind the separation between the planar windings and the core as you mentioned. I am planning to have the top and bottom of the PCB be bare material. However the problem of spacing on internal layers applies e qually to where the edge of the board can touch the core. Whatever rule I end up with for the internal spacing will apply to this region as well.

Reply to
sea moss

sea moss wrote in news: snipped-for-privacy@googlegroups.com:

I would not attempt a multi-layer PCB with that level of isolation requisite. Your design should place a single "winding" on a single PCB. And other windings on their own PCB, then place a 5 mil sheet of "Nomex" brand transformer paper between them It is around 1 or 2 kV per mil.

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This is the right stuff. You can order rolls or sheets, etc, and then you can die cut them or have them die cut in the shapes you need.

This method also makes the entire "transformer" a serviceable device too, and one does not sacrifice an entire PCB assembly for one blown xformer winding.

Just an idea.

Reply to
DecadentLinuxUserNumeroUno

"Tim Williams" wrote in news:pec57a$q5j$ snipped-for-privacy@dont-email.me:

Bullshitzski. :-)

Potting detatchment opens the assembly up for failure. And a creeping conduction path is nearly always the failure mode. If not an instantaneous arc failure.

If NOT detached, you are correct.

However, many potting compounds have poor surface to surface adhesion and particualrly against shear force. Most require the assembly be "primed" with a media that binds to the assembly surfaces better than the potting, and then to the potting better than the potting would attach to those same surfaces bare.

I found another nomex...

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Reply to
DecadentLinuxUserNumeroUno

Good idea, I will definitely consider it. Won't you run into the same orig inal spacing issue at the pins though? For proper alignment of the stack o f PCBs the pins for each PCB should go through the whole stack. So then we have to mind the separation from one winding to the pins of the other wind ings. Unless there's another way to stack the PCBs that I haven't imagined .

Reply to
sea moss

sea moss wrote in news: snipped-for-privacy@googlegroups.com:

You can have open holes in the winding layers that require a pass thru, and the place silicone (teflon actually) tubing over the pins. Then you could use transformer wire leads (instead of pins) to go to better spaced holes on the main assembly or wire direct to the HV destination. Then, the LV primary could be the place where the LV and stationing holes/pins go. The secondary and feedback pcbs (if applicable) could be where the double strength (or even kevlar) coated xformer wire would get used. Or even Teflon sheathed "HV wire" with SPC inside.

Reply to
DecadentLinuxUserNumeroUno

kapton seems stronger.

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Reply to
Jasen Betts

Yeah something like that would work. Keep in mind that the LV pins would n eed just as much isolation from the HV windings too, so all pins would have to be insulated. But this is adding a couple more manufacturing steps whi ch I was trying to avoid... I guess I could draw this all up and have a mag netics house build it for us. A better case would be to use something like 100V/mil on internal trace/pin/core spacing, because the prepreg won't del aminate...

Reply to
sea moss

There are some numbers in here:

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They mention 800 v/mil internal to FR4, but that sounds ambitious.

The do talk about planar transformers.

--

John Larkin   Highland Technology, Inc   trk 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

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Good to have another reference, thank you. The section on planar transform ers basically says that you can forget about using FR4 for simultaneous hig h current and high isolation, and go to high voltage polyimide film instead . I don't need high current but that construction might be useful anyway.

Reply to
sea moss

Just for insight, is it integrated magnetically? Because that is hard on a planar, you need to do asymmetric leg windings

About the isolation of FR4, our Q guy told me a couple of years ago the for SELV you need 0.4 mm prepeg in z direction

X direction if pottet you can look up in the UL standard tables.

Cheers

Klaus

Reply to
Klaus Kragelund

a planar, you need to do asymmetric leg windings

By integrated you mean having more than one lumped magnetic element on the same core? Like transformer and output chokes integrated? In that case, n o, this is a transformer with multiple secondary windings, some of which ne ed 3.5kV isolation between them.

or SELV you need 0.4 mm prepeg in z direction

I'm concerned with the x direction between internal traces on the same laye r; so potting doesn't apply. (Except that maybe I can hand-wave and say th at the potting will help prevent the PCB from any future delamination)

Reply to
sea moss

Coilcraft makes some nice planar transformers. The power density is insane.

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--

John Larkin   Highland Technology, Inc   trk 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Yeah I've got one of those on my desk at work, I dig the look of that "bus bar + kapton" or whatever it is, maybe that's the HV polyimide film mentioned in the other reference you posted.

Reply to
sea moss

n a planar, you need to do asymmetric leg windings

e same core? Like transformer and output chokes integrated? In that case, no, this is a transformer with multiple secondary windings, some of which need 3.5kV isolation between them.

Integrated means, for the LLC resonant converter case, that the leakage ind uctor is embedded in the transformer construction. You need about 20% leaka ge, which is easy on a regular transformer (just pull the windings away fro m each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction

for SELV you need 0.4 mm prepeg in z direction

yer; so potting doesn't apply. (Except that maybe I can hand-wave and say that the potting will help prevent the PCB from any future delamination)

Reply to
Klaus Kragelund

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