- Vref has a series resistor, and you put an R+C from opamp output to -in, right? :-o
- You've got a gain of 1.5 with the level shifter, which is alright. As others mentioned, Q1 could stand a zener.
- No current limiting whatsoever. In fact...
- The PMOS is wide freaking open. What gain is it operating at? Who knows!
Datasheet looks like it's down in the subthreshold region, where Id ~ exp(Vgs-Vpo), maybe 100mS tops, at the current shown. But it goes way up from there at higher Id, and there's nothing to prevent excessive Id.
If the gain is 100mS and the load is, say, 200V / 10mA = 20k, the gain is around 2000.
Add to that, the single pole of 0.1uF * 20kR = 2ms, and you've got 2000 times more gain, and less than 0 degrees of phase margin, around that poor opamp! (Remember, you only have 90 degrees to spare, and you lose all of those where the 0.1uF looks like an ideal integrator.)
One more crinkle: match up the opamp's output range with the level shifter's range. If it's swinging +/-15V, divide it down to -15V instead of 0V, so that Q2's emitter range is -7.5 to 0V (or rather, the Thevenin output from the divider). Or slightly up to ensure an off-biased state.
Using the same principle (matching operating ranges), Q1 should have a source resistor (fixing its gain ~constant, except near cutoff), and R1 could have some idle bias in it so there's minimal deadband coming up from cutoff.
As long as you don't mind a fairly high dropout voltage (about 10V for R1-R3 as shown), current limiting is also automatic: it's never higher than (V(R1)
- Vgs(th)) over (source resistor). A zener, to enforce V(R1) maximum, provides further assurance of this.
With these changes, it's easy to see the block diagram equivalent: Q1-Q2 is a transconductance source, current proportional to opamp output; the 0.1 and the load is the "plant", a simple single-order one, so an R+C compensation network allows full freedom to set a 2nd order control loop of desired damping.
Oh, check the gate-R1 time constant, too. If it's too slow, you have another pole in the loop (and don't forget Miller effect!), and you won't be able to stabilize it anywhere near as fast as the output capacitance would suggest. Make sure this is less than 1/3 the load or controller time constant.
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Website: https://www.seventransistorlabs.com/
"George Herold" wrote in message
news:f086a724-cd0e-45dc-ad46-7cfa3bc8cc45@googlegroups.com...
>
> Hi all, another circuit fumble on my part.
> I copied this circuit fragment from whit3rd... part of thread is pasted in
> below. Here's the circuit I built.
>
> https://www.dropbox.com/s/skaspzjafoqmcfl/HV-control.JPG?dl=0
>
> I ground the base of Q2 and added R3 so that it would start out with the
> HV turned off. D1 was added because I was worried about the zenering
> Q2's base. (opamp has +/- 15V rails.)
>
> Here's a scope shot of the output (AC coupled Chan. 1) and the emitter
> (chan 2.) I'm pulsing the Fet on for ~10 usec. every ~800 usec.
>
> https://www.dropbox.com/s/eoszsjj16dsn86r/Vout-E.BMP?dl=0
>
> I tried adding R's and or C's here and there in hunt and peck fashion.
> but without much change. The cycle time is mostly set by the output
> cap (0.1 uF) and load resistor (100k ohm)
>
> Sooo.... Am I doing something stupid, is there some way to fix it, or
> should I scrap it and start with something else?
>
> Thanks
> George H.
>
>
>
> *** previous post********
>
> Subject: Re: Abusing the LM386
> From: whit3rd
>
>> Thanks, I need pretty tight control. Some fraction of a volt out of
>> 300.
>> My brute farce idea looks like this.
>> https://www.dropbox.com/s/mfqhln20x7tkfk3/10-300V.JPG?dl=0
>
> A series pass transistor is a less heat-producing option: the level
> translator Q1 needs HV rating, but the pass transistor Q2 is just to
> take off the ripple, so 100V should be plenty:
>
>
>
> You can embellish it, of course; a collector series resistor//capacitor
> will
> share the heatload with Q1, and a source series resistor will limit
> shortcircuit current. Vbb* (R2/R1) is the gate drive limit.
>
> Optos are slow, it's better to draw the milliamp or so from the HV, at
> 300V. I think.
> Different, though, if it were 3 kV.