I've completed layout of a PCB which includes a PLL which phase locks a VCXO to an external standard. I was planning on setting the PLL loop bandwidth at a few Hz; but I'm worried that it won't be able to remove 50 Hz mains hum pickup. I would prefer not to electrostatically screen the circuit.
It's all SMT on a 2-layer FR4 board with an almost continuous ground plane. The PLL circuitry occupies a square inch of board area. Between an op-amp active loop filter and the VCXO control input I have an RC filter of 10k and
100nF using 0603 components mounted close to the VCXO.The specified phase noise of the VCXO at 50 Hz offsets is equivalent to 4uV peak at the control input. Am I likely to see much more than a few uV of 50 Hz pickup around that circuit node?
TIA Andrew.