I need to make a transformer for a push-pull converter. The core is a 25.3/14.8/10 toroid made of N87, f=200kHz (total, 100kHz per switch), Bmax=100mT, PRIMARY_Irms=10A, PRIMARY_V_MAX=20V. This gives 2x5 turns and this low value opens many options.
5 turns, each turn close to one another, then the other 5 turns the same way. Pros: thin winding, short supply wires.
5 turns across the entire length of the core, then the other 5 turns in between the first winding's gaps. Should be as thin as the first one, better coupling. Cons: the center tap endings are far apart.
5 turns of a twisted pair of Litz wires. Cons: much thick, the center taps are far apart.
5 turns of a twisted bundle of, say, 20 two-color wires,* then the appropriate unbraiding.
It doesn't matter.
The second issue: does any standard current density matter at all in the case of such short primary wires? Even 1mm^2 (total area of the Litz wire/twisted bundle) results in negligible RDC and the I^2R approach seems more scientific than any industrial I/area rule of thumb. I should focus on minimizing RAC. Correct?
200kHz is a high enough frequency that skin-effect matters.
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recoomends 38AWG (0.1mm diameter) between 100 and 200kHz
Making the two windings as five turns of twisted pain minimises leakage ind uctance, but maximinses inter-winding capacitance.
The filaments in Litz wire are shuffled to make each current path equal. A twisted bundle might not work out as well.
It is going to matter, but you have to know a fair bit about where your pro blem areas are going to be before you can work out which choice works best for you.
Current density matters if you have enough current in the wire to get it wa rm.
The problem is that high frequency current doesn't use the whole area of a solid wire. With Litz wire you've got less copper cross-section in a given window area, but the resistive loss at a given high frequency is less if you fill the winding window with Litz wire.
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If you aren't dissipating enough heat in the winding to matter, you might s tart thinking about a more compact (and cheaper) transformer, but you will get heat dissipation in the ferrite as well, and permeability drops quite f ast at the Curie temperature (above 210C for N87)
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pdf
Transformer design can involves quite a few trade-offs.
I like this series of slides from the University of Colorado course, it uses the method of Lagrange multipliers to optimize (minimize) total copper loss for given transformer requirements
Yes, I know that. The question is not what wire I should use, because I am able to design it properly, but how to make the dual primaries correctly using a proper wire.
I am thinking of using 20+ twisted wires, then unbraiding and shuffling the endings to make the tap. Leakage inductance is the source of spikes on the MOSFET drains, but what harm could the capacitance do (without going to the extremes, i.e. causing resonance exactly where you don't want it to be)?
There will be a prototype, of course, but I want to avoid visiting dead-ends.
I'd say if you have enough resistance, that is length. And enough layers to stop heat spreading.
Yes, proximity + skin effects combined. But this part I can manage.
Sure, for example I am not going to use the optimal number of turns, because it is a multi-output PSU. Bumping the number of secondary turns requires a similar primary adjustment, and that increases B and R. But the additional losses are less than making the voltages too big and then dropping them to the desired level. Since the initial B=90mT,
127mT is still fine. The core is a tad too big, but once again I am geometry-limitated.
Here's how far I got: maxima file and a .csv based on mostly epcos datasheets. no idea if any of this is correct
-------------------------------xfrmr.mac--------------------------------------- /* try to guess the power capability of the cores. using the AP estimate in slup126.pdf
/* the pm is a tad too big (3000W vs 520W) They(EPCOS) don't include the ring cores in their simulation tool want something more detailed.. The plan:
1)guess rtherm from v/surface
2)calc deltaB and currents for equal dissipation Pcore=Pwinding
3)check the temp rise is ok
1)R_th (EPCOS Ferrites and accessoires) R_th ~=1/sqrt(V_e) (a point from their R_th graph) R_th(300e-9 m^3)=100K/W
100=K/sqrt(300e-9) K = 0.0547722557505166 therefore:
*/ R_th(V_e) :=0.0548/sqrt(V_e); delta_T(P_v,R_th) :=P_v*R_th;
/* transferrable power: Ptrans=C*delta_B*f*A_e*A_n*J A_N is copper cross section m^2 A_e is core cross section mm^2 J current density A/m^2 C=1 for push pull delta_B flux dens variation Vs/m^2 f freq 1/s
Power loss: P_v=P_vc+P_vj P_vj=I^2*N*R_cu P_vc(B,f)=K*f^(1+x)*B^(2+y) x,y 0..1 delta_B=V*t/(N*A_e)
find the koeff K and exp y for core loss logexpand:super B,P
y=k*x+d y=log(P) k=dy/dx x=log(B) d =? d = 8.781048544054926 log(P)=2.42*log(B)+8.7810485 P=6509.699302573376*B^(2+0.420562799417347) y=0.4... try again for K K=3.398769238238504E+7
30e3,30e3
300e3,600e3 dy/dx= (log(600e+3)-log(30e+3))/(log(300e+3)-log(30e+3));
1.301029995663981 d = - 3.103303974733933 P(f):=K*f^(1+0.301029995663981) K = 0.04490060658064694 P_f(f):=0.04490060658064694*f^(1+0.301029995663981)
now how2 combine? P_vc(B,f)=K*f^(1+x)*B^(2+y) K=guessed 11.4
*/ P_vc1(B,f):=11.4*f^(1+0.301029995663981)*B^(2+0.420562799417347); /* winding losses: want those in terms of window area. filling factor 0.4
*/ P_vj(I,l,rho,A_n):=I^2*l*rho/(A_n*0.4); /* more accurate l based on inner and outer winding radius circular bobbins: fullratsimp(integrate(2*%pi*r,r,r1,r2)/(r2-r1)); l=%pi*r2+%pi*r1;
ring cores: l1(h,da,di):=2*(h+da-di); l2(h,da,di):=2*(da/2+di/2+h+di); l(h,da,di):=(l1(h,da,di)+l2(h,da,di))/2;
delta_B(V,T,N,A_e):=V*T/(2*N*A_e); B(delta_B):=delta_B/2; P_vc(f,V,N,A_e,V_e):=P_vc1(B(delta_B(V,1/f,N,A_e)),f)*V_e; /* assume p and s winding same voltage + current if I keep P=u*i const what's the opt u/i, N with min loss? P_vc increases times 2^2.5 for half N, double v, half core area increases times (2^(1.3))/(2^(2.5))=0.43 for twice f P_vj incr times 4 for twice I, 2 for 2 l, 0.5 for twice A_n
about the winding itself: The layered windings have higher capacitance but lower leak inductance sectioned ones have higher leak inductance and lower winding capacitance. There's some formulas in the Transformer and Inductor Design Handbook (google will find a pdf)(but none for toroids) slup126.pdf is also interesting, but careful it seems to use the cgs System. for guessing an rtherm, Epcos' PDF_Application.pdf uses 1/sqrt(V_e)
inductance, but maximinses inter-winding capacitance.
Simple twisting doesn't give you Litz wire. You want each wire to cut the s ame amount of magnetic flux, and single twisting doesn't give you that.
The inter-winding capacitance has to be dischraged and recharged whenever t he polarity flips. If you want to switch fast, that's a lot of current duri ng switch-over (when the voltage across your switching transistors is high) and it pushes up your switching losses and radiated interference.
Baxandall resonant inverters finesse this (which is why Baxandall invented the circuit) but the approach isn't popular if you aren't trying for high t urns ratios.
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problem areas are going to be before you can work out which choice works b est for you.
t warm.
Heat spreads quite quickly between layers of copper wire. Everything else h as a much higher thermal resistance.
Primary impedance is very low, count on heavy interleaving. Consider transmission line transformer design: not because of the bandwidth, but because of the method to obtain low impedances.
Ideally, primary Zo is around 2-10 ohms, depending on exactly what you meant (is V_MAX what the switch sees, or what the CT sees?).
Litz is lower losses but higher inductance. Consider that the whole point is to allow flux to penetrate the cable. This gives higher impedances, which may increase losses elsewhere.
Ideally, you'd have flat ribbon shaped Litz, so you get the paralleling and interleaving basically for free. It's out there, but regular Litz is already hard to find... :(
Yes, Rac matters, to the extent it may cause the transformer to overheat. No need to have it stupendously low or anything.
Last time I did something like that, I used 6 strands of #24 in parallel. Alternating for each side of the primary, P1-P2-... in a flat (multifilar) winding for the whole primary. Strands are connected to pins alternately, giving the interleave and CT winding. Leakage so low (between ends of the primary), I didn't even need snubbing for it -- the transistors are switching slower. (Slower than I would've liked; they were unfortunately limited by the inductance of the current sense resistor.)
What's secondary? If same voltage, throw another set in the bundle, interleaved, and you're good. If high voltage, consider that you need to keep its impedance high, otherwise it'll be swamped by capacitance.
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/
"Piotr Wyderski" wrote in message
news:pk3lkq$3te$1@node2.news.atman.pl...
>I need to make a transformer for a push-pull converter.
> The core is a 25.3/14.8/10 toroid made of N87, f=200kHz
> (total, 100kHz per switch), Bmax=100mT, PRIMARY_Irms=10A,
> PRIMARY_V_MAX=20V. This gives 2x5 turns and this low
> value opens many options.
>
> 1. 5 turns, each turn close to one another, then the other 5 turns the
> same way. Pros: thin winding, short supply wires.
>
> 2. 5 turns across the entire length of the core, then the other 5 turns
> in between the first winding's gaps. Should be as thin as the first one,
> better coupling. Cons: the center tap endings are far apart.
>
> 3. 5 turns of a twisted pair of Litz wires. Cons: much thick,
> the center taps are far apart.
>
> 4. 5 turns of a twisted bundle of, say, 20 two-color wires,*
> then the appropriate unbraiding.
>
> 5. It doesn't matter.
>
> The second issue: does any standard current density matter at all
> in the case of such short primary wires? Even 1mm^2 (total area
> of the Litz wire/twisted bundle) results in negligible RDC and
> the I^2R approach seems more scientific than any industrial I/area
> rule of thumb. I should focus on minimizing RAC. Correct?
>
> Best regards, Piotr
I can use 7x0.3mm TRW Litz for that purpose, 3 strands of it would give me ~1.5mm^2 cross-section per half-primary and a flat winding. Sounds very reasonable, thanks!
There's a whole herd of them. 3.3V, 5V, 9V and 18V are the main outputs, totalling to ~60W. There will also be a lot of 10V isolated low-current secondaries for high-side MOSFET drivers. I'd like to check a push-pull first, because it makes the life of the filters easy and I could steal some AC to directly feed several magamps in the critical places. A kind of "one ring to rule them all" approach.
A mundane active-clamp forward is waiting as a relief force. I would like to try the push-pull first also because of its neuron de-rusting merits. I haven't made a high-power push-pull for 15 years. Only the SN6501/IR21531 1W-class gizmos.
UCC28084, f_osc=224kHz, V_IN=10V (desired range: ~8..20V), no feedback to force 50/50 mode, no secondary windings. R_SENSE=50m, output switches: SQJA62EP-T1_GE3, input cap:
150uF/35V SMD polymer tantalum with 70m of ESR. 3D construction to minimize the lengths of the wires, ~1cm transformer leads soldered directly to the cap/drain tabs. BAT83 30mA diodes between D and S, just in case. No gate resistors. Core is B64290L0618X087, 25mm OD toroid made of N87.
Trafo #1: 1x7 turns, 20x0.335mm wires twisted together and then unbraided to make the center-tap primaries. Spread evenly across the core. Considered the best I can do.
Trafo #2: 2x10 turns of 0.7wire, the first half, the tap and then the second part, wound tightly. The worst possible implementation, just for reference.
Results:
Idle current=54mA for Trafo #1, 39mA for T#2. Looks like the effect of the increased capacitance Bill wrote about.
Gate signals: perfect, sharp, no ringing.
Drain waveforms: strange in both cases. With T#1 and T#2 I have massive ringing, but only on one of the drains. It's not an output stage issue. If I swap the primary endings, nothing changes. If I swap the gate signals, the ringing goes to the other coil. So it originates in the controller itself.
With T#1 it is always like that:
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With T#2 it started more symmetric:
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But by manually squeezing/stretching the primaries I am able to restore the T#1 situation, i.e. dampen the blue waveform. I am not able to significantly alter the yellow ringing, though.
50V of ringing in a 10V-powered push-pull looks scary. Moreover, it continues for the entire off-period.
Duty cycle is too high, limit it to, say, 45% (per output) or thereabouts.
No idea what the BAT83s are for, they're at best resistors when forward biased if ever. At worst, tiny fuse links when pushed slightly harder. :-)
Shittons of outputs aren't too bad for forward converters, but don't expect good cross-regulation, unless you can make them all very tightly coupled!
The classic ATX supply solves this by regulating 3.3V separately with a mag amp (as you're probably well aware :) ).
You may find it's better to use a main supply (e.g., the 18V?) and derive the others with DC-DCs (possibly with multi-windings or taps, to get certain "lucky" pairs of voltages, or negative rails if necessary, etc.). Depends on requirements, including size and cost, regulation, etc.
It was the first low-power Schottky I found in the box. I'll check with something better later. I'm also going to check Zener clamping just to see what happens (on a good way to invent a MINIMELF LED?)
Only the 3.3V rail needs good regulation, 9V needs to be decent (+/-0.5V is fine) and the 18V rail just needs to be there, as it is intended to power a 10W D-class audio amplifier with.
8..20. That would require a buck-boost to get 18V and functional isolation is highly welcome. For that reason another option is to produce that 18V with something isolated and then go down with a bunch of SOT-23 synchronous bucks from TI. Will work for sure, but there would be no fun. ;-)
I'm willing to spend some time on this approach just to learn something.
Most likely pulse width imbalance, leading to "flux walking" as it's colloquially called, but it's just DC imbalance, not some arcane bit of magnetic physics.
Reducing duty gives a high impedance period where the transformer can resolve its flux.
Better to do an RCD clamp snubber (one diode and one cap, each side; tie together the cathodes and use one resistor back to VIN). Downside: wastes idle current, so efficiency is crap at low output. May or may not be a concern. There are other similar approaches.
Simply winding the primary well is the best, but that's not always possible or practical, especially with transistors being as fast as they are these days.
Right, you also don't want to do that for a 20V maximum input. 30V TVSs would be better, or a clamp snubber, or quasi-resonant snubber if applicable, etc.
Or you can reduce switching time, effectively burning that power in the transistors. If you already need to heatsink them, that's not a big deal.
May I add one more question on push-pull transformers? How do I choose indu ctance of primary coil? The datasheets for LT1533 and LT1683 say: "The inductance of the transformer primary should be such that LO, when reflected into the primary, dominates the input current. In other words, we want the magnetizing current of the transformer small with respect to the current going through the transformer to LO. In general, then, the inductance of the primary should be at least five times that of LO. This ensures that most of the power will be passed through the transformer to the load. It also increases the power capability of the converter and reduces the peak currents that the switch will see."
I don't this recommendation. L0 is inductance of the output filter. First s entence says L0 should dominate (that is: larger L0 compare to Lpri - the b etter), but the third says Lpri should be "at least 5 ? LO/N^2" (th at is: large Lpri compare to L0 - the better). What is physical meaning beh ind that recommendation?
Read it closely: LO _current_ should dominate. Inductance is inverse with current, therefore LO should be >5 times smaller than Lpri, as it goes on to say.
A 50% duty cycle is incompatible with break-before-make switching.
It takes a finite time to switch a MOSFET on or off - you've got to move a finite amount of charge into or out of the gate electrode - so a 50% duty c ycle implkes that one is turning off (but not turned fully off) at the same time as the other one is turning on (but not fully turned on).
This tends to produce nasty current spikes in the supply current.
At 100k - a 10usec period - a 45% duty cycle implies two 250nsec gap to cov er turn-on and turn-off, which ought to be generous.
With high current gate drivers 25nsec might be enough.
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