How to invert output of NE555?

How about a long duty cycle? This can be accomplished with a little signal diode stuffed in the timing circuitry.

Here is one page describing this:

Jon

Hey Slater,

Here's a circuit I came up with that hopefully will do what you ask:

At idle, the output pin is HIGH and the timing capacitor is charged up. The negative-going pulse applied to the RESET input brings the output low, and the capacitor discharges through the resistor until the voltage on the capacitor reaches 1/3rd Vcc; the output is low for this time. Then the TRIGGER input sets the output high again, and the capacitor is quickly charged up again through the diode to prepare for the next pulse.

In the picture the purple pulse is the negative going pulse on the reset input, and the green is the output.

The "low time" is approximately RC*log[Vcc/(3*(Vcc-0.6)].

What you're looking for is a delayed trigger ? If you're not using edge triggering, then supply the trigger with a R and shunt a cap to create a time delay on the trigger. The input of this circuit should be pulled up via an R from the Vcc to ensure proper charging of this cap for the next time cycle to be accurate or close to it..

If you are not using edge triggering, then you could use a 556 timer (dual). The first stage to be used as a time delay for the second stage on the trigger..

Jamie

No matter what all the youngish try to do, they just can't kill the use of a 555/C555 timer :)

Btw, that's a nice page.

Jamie

Thank you all! I'll try Bitrex's solution, it's just what I need.

What was his suggestion? The post didn't show up here for some reason :-( ...Jim Thompson

-- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

Remember: Once you go over the hill, you pick up speed

Here ya go:

Negative going pulse at RESET gives a negative going one-shot at the output, the "low time" is approximately RC*log[Vcc/(3*(Vcc-0.6))].

On Sat, 26 Mar 2011 10:10:03 -0700, Jim Thompson wrote:

--- Version 4 SHEET 1 880 704 WIRE 32 176 16 176 WIRE 272 176 256 176 WIRE 32 240 0 240 WIRE 320 240 256 240 WIRE 320 288 320 240 WIRE 32 304 -112 304 WIRE 32 368 -208 368 WIRE -336 432 -336 384 WIRE -208 432 -208 368 WIRE -112 432 -112 304 WIRE -80 432 -112 432 WIRE 0 432 0 240 WIRE 0 432 -16 432 WIRE 320 432 320 368 WIRE 320 432 0 432 WIRE -112 464 -112 432 WIRE 320 464 320 432 WIRE -336 560 -336 512 WIRE -304 560 -336 560 WIRE -336 592 -336 560 WIRE -208 592 -208 512 WIRE -208 592 -336 592 WIRE -112 592 -112 544 WIRE -112 592 -208 592 WIRE 320 592 320 528 WIRE 320 592 -112 592 WIRE -336 640 -336 592 FLAG -336 640 0 FLAG -336 384 +5 FLAG 272 176 +5 FLAG -304 560 0V FLAG 16 176 0V SYMBOL Misc\\NE555 144 272 R0 SYMATTR InstName U1 SYMBOL voltage -208 416 R0 WINDOW 3 24 104 Invisible 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR Value PULSE(12 0 0 1e-7 1e-7 1e-6 0 1) SYMATTR InstName V1 SYMBOL res 304 272 R0 SYMATTR InstName R1 SYMATTR Value 47k SYMBOL cap 304 464 R0 SYMATTR InstName C1 SYMATTR Value 4.7e-7 SYMBOL voltage -336 416 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 WINDOW 0 23 10 Left 0 WINDOW 3 24 104 Invisible 0 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL res -128 448 R0 WINDOW 0 -40 54 Left 0 WINDOW 3 -44 83 Left 0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL diode -80 448 R270 WINDOW 0 32 32 VTop 0 WINDOW 3 0 32 VBottom 0 SYMATTR InstName D1 SYMATTR Value 1N4148 TEXT -128 632 Left 0 !.tran 1

-- JF

What is that in ASCII?

Sorry, should be -RC*log[Vcc/(3*(Vcc-0.6))].

on

=A0 =A0 =A0 =A0...Jim Thompson

That is a monostable - the only potential problem I see is there should be a 10K, or so, to GND from the THRESH input, otherwise it will work great.

The reset goes low, and then the output goes low for a time determined by an RC network. So it's the opposite of the standard 555 monostable, where the trigger input is pulsed low and the output goes high for a time determined by an RC network. Sure, it won't work if the reset isn't held low long enough, but I don't see why the reset input would need the pulse to stay low any longer than the trigger would with the ordinary monostable in the standard configuration.

The OP says it satisfies his requirements, so I'm not sure what the problem is.

Good catch - that will keep the threshold from accidentally floating up to a high level and messing things up. Hopefully the OP sees your correction.

This:

The op wanted a Monostable not a Time delay on.. Also, that circuit won't function if you don't hold the RESET low long enough..

Maybe I am over looking something but It sure does not look like what was requested. A monostable turns off when the Threshold is reached. A time delayed one-shot/monostable.

Jamie

Sure, when the Threshold is being used. What I see there, it's not even connected.. So, it's not monostable at all.. Just a time on delay.. On top of that, the Reset pulse must be shorter than the mono cycle and the off duration long enough to fully discharge that cap! problems, problems...

Jamie

son

=A0 =A0 =A0 ...Jim Thompson

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The OP said "...but stays low for a second... ", so it /should be/ unlikely that the trigger is still applied during the timeout. It is monostable in the strictest sense, assuming the RST trigger is lifted, because the TRIG is tied to the timing capacitor heading towards 0V and thus a threshold crossing of the TRIG input causing the output to flip back H where it will remain indefinitely - the mono-stable state, until retriggered via RST.