How quiet are ADCs and DACs on micro controllers?

Hello All,

There are some data sheet entries stating the SNR, for example for the

16-bit converter on the MSP430F2013. However, it isn't too clear what kind of code it was running at that time and in my experience it is rather difficult to get that information out of manufacturers.

Anyone with noise experience? How about the DACs? How much noise would be riding on them if you held their data register constant and looked at the analog out?

Other than for mundane 8-bit jobs I always used external ADC/DAC in the past but with newer devices there are often not enough port pins to do that. I could measure it and still hit a snag. Just want to avoid the situation where I am told after tons of work "Yeah, but you should not have accessed the HW multiplier thingie during integrate and hold" or something like that.

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg
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Well, the biggest issue is PSRR of the internal components, and whether they are separated from the main power supplies.

Like you, I don't trust the ADC/DACs in microcontrollers for anything except mundane, non-critical things. Therefore, I have never characterised microcontroller ADCs/DACs as I simply use them where noise is not a major issue.

Cheers

PeteS

Reply to
PeteS

Joerg wrote:

Sometimes it takes perseverance to get the information you need. I looked at the datasheet and there are testing conditions stated for the SNR of the ADC. That is usually all the information that will be given up front. In my experience (junior engineer here), manufacturers hesitate to give out numbers that are not explicitly in the datasheet. Through my discussions with several manufacturers the line of reasoning is this: Even if you were to wrench out test data from one of the senior application engineers or even a designer, the data given is considered to be a 'typical' and not a MIN or MAX which should be guaranteed. The data usually comes from a test set up where a part was placed in the configuration you asked and tested. It is not production tested nor is it characterized. So you are given a number and go off to purchase x thousands of devices. A large percentage of these devices do not meet the test data you received. WTH?! Well, the hell is that it is not a guaranteed spec. There is not that lovely Gaussian distribution that can be found when designed to a spec or characterized through production tests. So manufacturers usually put the onus on you to test. Unless someone has an idea of how much noise to expect, I would test it in my own circuit and hopefully I will be comfortable with the results. I would lean toward the idea that the ADC is 'isolated' from any other internal sections of the micro-controller. Could be wrong...all devices are different.

Reply to
Kingcosmos

This hesitation to give out additional info can also have legal reasons. It seems that mfgs have become much more fearful there. Recently I had a part that misbehaved under certain conditions (sudden load changes) and this was not mentioned in the data sheet. So I sent them the schematic and all but I was unable to convince them to throw that onto SPICE together with the model of their part, which I can't do because they won't disclose that model. Maybe they were afraid to find a rat somewhere in the innards of the chip, who knows. Instead they insisted on scope plots which were nearly impossible to provide because the lock-up and subsequent kablouie happened only occasionally.

I have also tried numerous times to get more info on uCs such as the MSP series. Nada, zilch. It felt like kicking a big oak tree. Nothing beyond what's published already. Suffice it to say that it has cost them several design-wins because I decided to go the analog route like usual.

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg

Much is dependent on your layout. I'm not too familiar with the mentioned family to go into details. Try averaging to reduce the noise if cpu-time permits.

Rene

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Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
Reply to
Rene Tschaggelar

I doubt they can produce it. It depends too much on the usual suspects (board layout, decoupling, running code, frequency, etc, etc). I'm quite sure though that the specs in the datasheet are produced in a best case scenario (which may be a simulated environment).

I think creating a test circuit and do some measurements is the only way to know for sure.

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Reply to nico@nctdevpuntnl (punt=.)
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Reply to
Nico Coesel

Hello Rene,

The layout will be RF engineering style. I am more concerned about things on the chip itself. That's behind the bond wires where there is not much I can do other than averaging and making sure that segments of the uC are not jerked on and off in terms of power consumption.

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Regards, Joerg

http://www.analogconsultants.com
Reply to
Joerg

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