How does a PLL work?

The vital difference is that the response of the integrator is proportional to the amplitude of the input. Small input -> small output slope. Big input -> big slope.

Counters have a fixed slope for a fixed update rate. An integrator is like a multiply-and-accumulate stage, i.e. a 1-pole IIR lowpass.

Cheers

Phil Hobbs

The locking phase will depend on the frequency offset, though, which may give rise to phase wander on thermal time scales due to VCXO drift. A second-order digital loop would fix that, I expect.

Well, the practically-nobodies obviously congregate on the lunatic fringe. ;)

First-order loops are rarely used in RF stuff, anyway.

Cheers

Phil Hobbs

Simple first-order PLLs work just fine if the VCO and reference already have the same frequency. If you want frequency-locking _and_ phase-locking too that'll cost extra!

Why? Phase locking doesn't have to be at 0 or 90 degrees to be phase locking--the relative phases just have to stay still.

Cheers

Phil Hobbs

With a first-order PLL there's some kind of Heisenberg-uncertainty-type-thing going on; if the frequency is locked then the phase must be unlocked or how could the frequency be locked? If the phase is locked then how could the frequency be locked?

Well, I just don't see anywhere in the equations for such a PLL where the VCO control voltage input being constant materially implies that the reference and VCO instantaneous frequencies must be equal, just that the integral of their relative error be constant. And if the control voltage should not be a constant then I don't see how the phase can be truly locked, either...

I guess what I'm trying to say is it's assumed in the analysis that the VCO gain is not a function of time, but that's not really true.

Think again: Frequency offset is the rate of change of phase difference. If phase is locked, frequency must be also.

I just want the frequency to be right. There will be ground loops and stuff from the reference, so we want a slow, no-drama loop.

I also assume that if the customer doesn't give me a 10 MHz reference that's right to 1 PPM absolute, there's no point to locking to it.

Most VCXOs and OCXOs lowpass filter their VC input, in the KHz range, but that's outside out basic integral range, so our XOR loop is pretty much still 1st order.

I have done PLLs where the phase mattered, to picoseconds. Those used an ECL Dflop as a bang-bang early-late phase detector, which is mathematically nasty.

One can have distinct acquire and track gains or time constants. Wideband when out of lock, narrowband in operation.

In Analog it's done by having the phase detector output a current into a capacitor ^1 (at zero error/current, the capacitor "holds" its present voltage).

^1: Actually implemented by a capacitor with a series resistor to produce a loop zero... since the VCO itself presents a loop pole.

Mathematical purity often misses reality's impurities ;-) ...Jim Thompson

Ya but in the simple XOR phase detector -> loop filter -> CV output setup the loop doesn't have the actual instantaneous phase offsets of both the sources (as compared to some perfect third reference I guess) as data to compare to generate the error voltage; it's first generating sum/difference _frequencies_ in what amounts to a binary multiplier, filtering to get the difference, and then the VCO itself acts like an integrator to obtain relative phase error from the difference frequency.

AFAIK all that's required for the system to "believe" it's in lock wrt both frequency and phase is for that integral to be constant, but the constant is finally arbitrary.

That is to say in that scheme for a phase error voltage to be generated at all there must be an instantaneous frequency difference. If there is no instantaneous frequency difference at all and the CV output is outputting a constant for eternity then who knows what the relative phase of the references are? If all you had was the CV output to "look" at as your data set and the rest of the circuit was a black box how would you know? Ok, they're locked...to...something.

Perfectly willing to accept I'm wrong in this "analysis", but if so I'd like to know where! ;-)

The math shows that to design a PLL of the type he's designing that simultaneously locks instantaneous frequency and phase you need a delay line/memory of infinite length. The math is right!

"Lock" indicators are notoriously flaky. For those customers who want such an output I usually define it as a defined number of successive charge pump slivers less than a designated width.

Built any working PLL's recently ?>:-} ...Jim Thompson

If you must respond to my posts please do not delete portions of my post that negate your "infinite wisdom".

I have no idea what you mean by, "The math is right!", but you're wrong about practical implementations >:-} ...Jim Thompson

In the OP's second paragraph he lays out the problem with his digital PLL of this topology, where he notes that without an infinite memory the VCO has a tendency to want to drift back towards its free-running frequency.

My point was that AFAIK that's not unexpected; at least I don't see it explicitly saying anywhere in the couple books I have which have sections on PLL design that you get perfect frequency locking "for free", too. If you want a low-jitter frequency lock as well then as a designer that's on you. The books aren't "lying" exactly it's probably just a "things they ain't say" kind of situation.

I designed a frequency-locked-loop multiplier to generate some clocks using a 555, a TL431, and a bit of glue logic (163 counter, NAND gate crystal oscillator/xor multiplier) a while back and it seems to work well enough for being under $1 worth of parts; a frequency locked loop is a simpler task

Things sure are strange in the digital Cretaceous today!

Cheers

Phil Hobbs

I've seen all those words before, but never in that order. ;)

You're going in circles. It's only the relative phase that matters. The way to analyze it is to average the relative phase over one cycle of the reference, find the stability conditions, and then introduce the ripple as a perturbation. You can use as many perturbation orders as you like.

But it has to sit still, which is how lock is defined. The relative phase needn't be 0 or 90 degrees for it to be in lock, as I said earlier.

Not at all. The output waveform of the phase detector has ripple (quite a bit of it if it isn't filtered). The ripple makes the instantaneous VCO frequency vary during a cycle, but all that does is distort the waveform depending on the locking phase. In other words, in a first order the relative phases of the harmonics of the VCO are different for different reference frequencies within the locking range of the loop, that's all.

That doesn't make the phase or the frequency indeterminate.

Well, you know it's constant, which is what "locked" means.

There are only two signals in view, so that tells you all you need to know: they're locked together, which is the point of the exercise.

Cheers

Phil Hobbs

Why do you think so? A digital PLL is perfectly simulable, in fact it always is a simulation, just fed with real data. In fixed point you can check the entire state space in several hours and be sure that your SWAGed parameters are the right ones. Cannot say much about their analog counterparts, but building one for the purpose of mains synchronization would be a bit crazy.

But you *are* able to say that, every step can be recorded. If the book says that the first order loop filter simulated by a leaky IIR integrator should have alpha=1/319, but the simulation shows the convergence doesn't happen, however for the tweaked alpha in the 1/10000 ballpark the loop is rock-stable in the entire band of interest + safety margins and it exhibits no detectable phase offset, then what value are you going to believe?

Best regards, Piotr