How does a PLL work?

Floyd M. Gardener "Phaselock techniques" ISBN 0-471-04294-3

The low pass filter between the phase detector and the VCO has enough memor y to do the job. With a first order filter it's trivial to amke it work, bu t even a second order filter adds enough extra phase lag around the feedbac k loop, when combined with the fact that the VCO integrates the phase error , to create a stability problem, as is discussed at some length by Floyd Ga rdner, along with the solutions.

--
Bill Sloman, Sydney

No it is correct, books that only write what you cite in the first paragraph are merely explaining the general principle and do not go down to the detail that you encounter when really implementing it. That does not make them lying, they just aren't complete.

Check the theory of a PID loop as well.

Quadrature phase detectors can lock at non-integer ratios. You need a frequency-phase detector to lock on the fundamental.

I don't want to sound pompous, but I dare to think that many/most of the authors are just copy-pasting their predecessors and have no clue what *really* happens under the hood. In the case of the multiplying detector the second harmonic is not a nuisance, an artifact of basic trigonometry, but actually the thing which makes it work.

Definitely a more diplomatic way to say that, but whatever you call them, they are misleading to the point which renders the implementation of a correctly locking loop impossible, if you follow the book too closely. I've lost a day trying to figure out why my "properly" designed loop goes mad, but manual tweaking makes it super-stable.

I think I would need to go there some day, because in the digital domain it seems to be much more natural to control the increments instead of the magnitude of some variable.

Best regards, Piotr

Isn't it just a matter of the pulling range, i.e. be a problem only in the case of wideband loops? If the VCO bandwidth is narrow, then it simply cannot reach the stable non-integer ratio. In my case f_c+/-10% is perfectly fine, but the exact phase tracking is the key figure.

The ones I am aware of are edge-sensitive, so for a low-frequency loop:

1. How would you get the input signal edge in the first place? A comparator with a preset level? No, very amplitude-dependent. Zero crossing detector? A tiny amount of noise will derail it.
2. There are too few edges per second at 50Hz, so the convergence will be sloooow.

The multiplier is a real-time (approximate) phase detector, you don't need to complete a full cycle to get meaningful results. Do you know a practical PFD with comparably low latency?

Best regards, Piotr

Like you, I have experienced this myself when I built a frequency synthesizer (VCO/divider/reference oscillator/phase detector) way back in the seventies, and I thought I could reduce the spurs by "improving" the loopfilter (relative to the example I found in a magazine).

Indeed, that did not work.

Thanks a lot for your confirmation that I am on the correct track, Rob!

Best regards, Piotr

PFD gives exact phase tracking with no non-integer lock ratios, locks only to the fundamental.

Zero cross. The loop filter will take care of the noise.

Depends on the loop bandwidth.

The results are not meaningful when the loop is out of lock. You are not going to get meanginful results on a partial cycle.

You can start the vco in phase with the incoming signal. In either case, XOR or PFD, the lock time depends on the loop bandwidth. You then set a limit to the allowable phase error and wait until it gets there. If it's not fast enough, increase the limit or the loop bandwidth. The latter will increase the loop jitter.

You're describing a _first_order_ PLL. Those lock up in 1 cycle, on the plus side, but on the minus side they have a lot of comparison frequency ripple and exhibit a phase error proportional to the difference between the reference frequency and the oscillator's free-running frequency.

But practically nobody uses those.

Normally you do one of two things: for low performance, use a frequency/phase detector with a tri-state output, such as PD 2 of a

74HC4046, or use an op amp integrator with a lead-lag characteristic.

Your average op amp has a DC gain of 90-140 dB, so that the static phase error goes away, at least down to the level set by the offset voltages of the op amp and phase detector.

A PLL measures phase and sets frequency, so it's intrinsically integrating. That means that (without a loop filter) its open-loop transfer function has one pole at zero, and -90 degree phase everywhere.

If you add another integrator, the phase is near -180 degrees, and the loop will oscillate. One simple way to frequency-compensate a PLL is, first, to calculate the frequency where the two-integrator transfer function crosses 0 dB:

w_0 = 2 pi f_0 = sqrt(K_vco K_phi/(RC)),

where K_vco is the VCO control gain in rad/s/V, K_phi is the phase detector gain in V/rad, and RC is the time constant of the integrator (i.e. R_in * C_f).

Then you put a resistor R_z in series with the feedback capacitor, forming a time constant C_f * R_z = 1/w_0.

That'll give you about a 52 degree phase margin, which is a good starting number.

The math isn't difficult. You'd probably like Floyd Gardner's classic "Phaselock Techniques", which has all of that stuff, written by one of the pioneers. (I usually find that the best books are written by the people who invented the technique, because in order to do that they had to have a simple idea of it.)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net

Nice analysis. You forgot the XOR can lock on non-integer ratios and deadband in the 4046. Easy to fix if you do your own PFD. DC offset to get away from deadband is not allowed.

For the filter, I prefer the following driven by a current source:

------------- | | --- --- | |------------- TP1 | | | / --- \ --- / | \ | | GND GND TP1 gives you the phase error during lock. You can see ringing and overshoot. This is important in octave-bandwidth loops.

I understand the edge-sensitive PFD with a charge pump. It is basically a counter incremented/decremented accordingly to the FSM state, which content can be directly transformed into phase error. But you've lost me here: and integrate what? And what should I do with the result?

Indeed, but the typically presented model is misleading. I'd say the first order PLL is in fact a distortion-locked loop and excessive filtering is the last thing you want. But the internet books/courses don't say that...

Thank you, will try to get a copy.

Best regards, Piotr

The books don't lie, it's just that in practice a PLL is one of those feedback/control systems where you can't twiddle coefficients in Spice or software and expect it to work well. It's a negative-feedback system with a ton of loop gain and like any other such system you can't just go on slapping poles into the loop and expect it to not be unstable; usually the VCO has a frequency-dependent gain, the phase detector has a frequency-dependent gain, and the loop filter has a frequency-dependent gain and they all interact.

So you have know your requirements and write down the loop equation including all those functional blocks in the s/z domain and apply all those fun techniques from control theory, and look at Bode/root locus plots in a CAS or something to ensure you have the performance you want while also maintaining sufficient phase margin throughout the desired regime of operation.

That is to say just blindly "tweaking" the loop filter order without being able to quantitatively say how that tweaking interacts with the rest of the loop isn't likely to lead anywhere nice. There aren't really any "cookbook" topologies that can be applied to wildly different requirements; if your requirements are significantly different than a ready-made circuit in a book it's back to the drawing board.

The charge pump is not a counter. It is an integrator. The voltage change is proportional to the phase error.

You are going to confuse yourself. Gardner is not going to help you much.

Get LTspice and study some loops using XOR and PFD. The math can help you find the filter component values. LTspice will show you how the loop works.

Ideally you could just use an op-amp integrator to integrate the output of the phase detector - phase detectors usually generate sum and difference components and you want the DC component of the error signal to drive the VCO and filter out the sum. But you can't naively insert a bare integrator into your loop because it adds a 90 degree phase lag, and you already have phase lag because the VCO itself is acting as an integrator, i.e. frequency is the integral of phase. So you have use a lead-lag type of integrator/filter that zeros out some of the phase shift in your area of interest

Sorry, swap that, phase is the integral of frequency ;-)

Conceptually they are the same. There is no difference in charging/discharging a capacitor from two opposite current sources and incrementing/decrementing a counter by a unit step based on the edge lead/lag between two signals. If done sufficiently fast, both results converge.

Best regards, Piotr

Incrementing a counter is a bang-bang loop. You are constrained by the resolution of the counter. That also determines the phase error at lock. The best you can do is +/- one LSB.

That is completely different from integrating a current pulse. The best you can do is zero.

These are two completely different loops.

On a sunny day (Mon, 25 Sep 2017 12:50:27 +0200) it happened Piotr Wyderski wrote in :

Exactly, well know every household case was the NTSC (or PAL) color subcarrier PLL (in every TV), usually a crystal that can be tuned by a varicap over only a small range by the color burst. No way will it ever lock on some 'harmonic'.

Well, I didn't mention the XOR. ;) The deadband on the 4046 (and the _horrible_ oscillator nonlinearity on all the HC versions from all vendors, including the "improved" ones like the 7046, is a topic that I've ranted on here several times in years past. The deadband is only a couple of nanoseconds wide, so usually a 1-M resistor to ground will pull the loop's operating point far enough to avoid it, without introducing gross amounts of reference frequency ripple.

The Motorola approach uses two separate outputs for up and down. They're chosen so they overlap slightly near zero degrees rather than disappearing like the 4046's single output.

That means that you have two intervals of a few nanoseconds where the sensitivity is halved, as one pulse disappears while the other gets wider. Crucially, however, that interval isn't where the loop actually servos, so it doesn't produce hunting as in the 4046. Way BITD (1981ish) I used an MC14152 synthesizer chip that worked like that.

I think JT's MC4044 works like that too. (It has a separate charge pump, which I've never used)

Yup. I often use /4 Johnson counters in PLLs so that I can have a cheap lock indication. I'm not a huge fan of the phase pulses output of the 4046.

I mostly use PLLs in one-offs, and most of them use diode bridges for phase detectors because they're quiet. For actual production instruments it's frequently cheaper to do other things.

A 1:1 PLL can do a wonderful job of cleaning up a spur-infested mess arising from direct synthesis and frequency multiplication.

But the OP is trying to do it in software. ;)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net