Holy wasted opamps Batman.

Not a true integrator, just a lowpass filter. The VCO is the true integrator.

Hey, I just said that!

The vco turns voltage into frequency, but the phase detector detects, well phase. Phase is the integral of frequency. It's the combination of VCO+Phase detector that becomes a voltage-to-voltage integral.

Most VCOs, specifically VCXOs, have a lowpass filter between the VCO analog input and the varicap. They really have to. That is typically in the 10 KHz range. So that lowpass filter cascaded with the inherent VCO phase integration makes that block 2nd order. The lowpass filter after the D-flop makes the loop 3rd order. But if KVCO is small (as it is for the usual VCXO with a small pull range) it's easy to have the integral dominate, and get a 1st order, dead stable loop. Of course, things like this have narrow acquire and lock ranges. Wideband PLLs are a lot different.

One thing that we sometimes do is to build a triggerable start/stop oscillator and, after it's triggered, lock it to a crystal oscillator reference, but keep the start/stop oscillator edges time-coherent to the trigger. The math can get boggling.

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John Larkin         Highland Technology, Inc 

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John Larkin
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OK thanks, I was just thinking about a low pass on the VCO input as the integrator. I'll have to think about that more. So the (inherent) time constant of the VCO is the frequency times some gain?

OK thanks again. I'm mostly an idiot about PLL's.

George H.

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George Herold

PLLs

One of my favourite tricks for handling that problem is to wrap a very weak positive feedback loop around the loop filter. When the loop is unlocked, K_phi drops to zero and the positive FB turns the loop filter into a slow t riangle wave oscillator. You have to make sure that df/dt

Reply to
pcdhobbs

That's cute, scan for lock.

I've done adaptive loops, switching between a fast filter when unlocked, to a slow filter after lock. If you have an FPGA in the loop, you can do all sorts of tricks, like using frequency counters to get close to lock.

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John Larkin         Highland Technology, Inc 

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John Larkin

Interesting. Self-sweeping. I'll have to investigate that. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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Jim Thompson

Phil,

How does K_phi go to zero? Do you mean the _output_ of the phase detector goes high-Z? More explanation, please. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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Jim Thompson

That provokes this idea:

formatting link

I'm not using the set or clear flop inputs. An FPGA could look at Q or Qbar and drive set and clear. It could do lock detection using some mumble-mumble algorithm, and take over and force (or PWM) the flop when the loop is out of lock.

An additional flop or two could do early/late detection and provide more info to the FPGA, but that's probably overkill.

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John Larkin         Highland Technology, Inc 

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John Larkin

It goes high-frequency.

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John Larkin         Highland Technology, Inc 

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John Larkin

K_phi is the short-time averaged PD sensitivity. If there's a beat note, it averages to zero.

Normal PD pull-in works by way of the beat note. Assuming the loop amp's ph ase isn't too large, on the ripple half cycle that tends towards lock, the beat frequency is less, so that half-cycle lasts a little longer, making a small DC component. Over many cycles, the loop amp integrates this till eve ntually the loop locks. Pull-in gets much weaker for larger beat frequencie s, which makes it vulnerable to offset voltages and such. There's also the phenomenon of false lock, where the loop amp's phase is too large, so the p ull-in signal goes to zero somewhere other than lock.

Cheers

Phil Hobbs

Reply to
pcdhobbs

Well, since you generally need the quadrature phase for lock detection (and maybe AM demod), a PFD works well too. You can make it a weak perturbation like the positive FB, or else turn it off when the lock detector gives the OK.

The sneaky-sweeper idea works great for laser cavity-locking too, where you don't even have a beat note.

Cheers

Phil Hobbs

Reply to
pcdhobbs

It does introduce a small amount of AM-PM conversion due to the resulting D C offset, which has to be a few times the worst-case offset of the PD and l oop amp. It wouldn't be rocket science to short the + input to ground when the lock detector says so.

Cheers

Phil Hobbs

Reply to
pcdhobbs

We talk from different view-points. K_phi is the phase detector _constant_. K_v is the VCO _constant_. (See Gardner.)

How is this _physically_ implemented to get your sweeping method? ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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Jim Thompson

t averages to zero.

'tain't constant though--it goes to zero far from lock.

I'm _quoting_ Gardner, from memory. See his discussion of pull-in.

Cheers

Phil Hobbs

Reply to
pcdhobbs

The positive FB usually comes from a Schmitt trigger as in the usual tri/square oscillator, with the Schmitt's output coupled to the SJ via a big resistor. There are other things you can do, but that's about the simplest. You get a little big of a barb on the tri wave due to the resistor in series with the feedback cap.

See e.g. .

Cheers

Phil Hobbs

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Phil Hobbs

The problem with that is that it'll sweep way too fast. It isn't sufficient for the two frequencies to be the same--the phase has to be close enough.

Cheers

Phil Hobbs

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Phil Hobbs

OK. I see what you're up to. I'll have to experiment with that and see what error it introduces.

What I usually do, when I need fast acquisition (*), is widen the bandwidth temporarily.

(*) Rarely. I'm usually just doing synthesizers now-a-days... all my analog loop stuff was so last century >:-} ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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Jim Thompson

The single-D _IS_ an early/late detector >:-} ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
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Jim Thompson

Since you have an FPGA, you could make a slow sweep by moving the set/clear edges. To it to lock reliably on the first pass, you need

df/dt

Reply to
Phil Hobbs

One might PWM the flop to get the frequency close, then turn it loose. Something like that.

We often use an FPGA pin, lowpass filtered, into a VCXO. We can wiggle it open-loop, PWM or delta-sigma, to trim the oscillator from a cal table entry when an external reference is not available. Then cut over to PLL mode when we have a reference.

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John Larkin         Highland Technology, Inc 
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John Larkin

Makes sense.

Cheers

Phil Hobbs

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