hints for design of a DDS?

AD9912 ($60) AD9914 ($160)

Both have 16-bit phase modulation. The AD9956 has 14-bit modulation, but you'd have to use it in a X4 configuration, which would lose you two bits of phase resolution.

Cheers

Phil Hobbs

What's the range of the phase modulation? +/- pi?

Thanks, that provides some material for reading. I do not require 16 bits of modulation resolution, but more than 4. The audio is available as 16-bit, but 14-bit should be more than adequate.

(it is just NBFM voice communication radio)

More resolution will not only make the audio sound better, but it should reduce the amount of wideband modulation noise.

Yup, except that after multiplication +- pi becomes +- N pi.

Cheers

Phil Hobbs

Since your modulation bandwidth is small, you could reprogram the frequency of a DDS chip at your 12KHz rate. A uP or a small FPGA could accept your digitized analog audio and spit out parallel or serial frequency-set data to a DDS chip.

You should probably clock the DDS pretty slow and mix its output up to

You could roll your own DDS with an FPGA and a DAC, and do all sorts of signals-and-systems math yourself. We've done that a couple of times and it was fun, like being back in EE class.

IIRC the usual communications-quality narrow-band FM is preemphesized, so that it is, in effect, phase modulation. What I don't know is what the phase deviation is.

So if you've got a DDS chip that supports modulating the phase, that may be the way to go. After some math.

:)

It has to be seen how quickly the DDS phase increment can be changed in real time. It depends on the architecture of the DDS chip (if any).

This is complicated by the fact that the output frequency should be derived from the 10 MHz reference. To do this, I would need two different synthesizers, one DDS to generate a low frequency modulated carrier and a classical dual-modulus PLL to generate a fixed frequency from the same reference.

I'm not sure this is a good idea. When I want to use a slow DDS it could be better to generate 1/3 or 1/4 of the desired 430 MHz and then just multiply the result using a nonlinear amplifier and filtering.

I am considering that, as there is another requirement not yet mentioned: the modulation should be time-synchronized to a pulse-per-second signal. This also requires some processing, that could be done with a processor or with an FPGA.

That is right. FM and PM are directly equivalent. The difference is just pre-emphasis, and it is already done in the system in a digital filter that processes the sample stream. I can turn it on or off as required.

I think the phase deviation can be calculated from the deviation (3 kHz at 430 MHz) and the maximal modulation frequency (about 3.5 kHz). Time to dive into the communications theory book...

That is a good point! Of course it cannot be filtered away, so this has to be closely looked at. Maybe there are chips that internally upsample to more bits? That would be required for GMSK as well.

You won't need to multiply, just use a BPF to do your antialiasing instead of an LPF.

The AD9912 that Phil mentioned can be used at higher Nyquist zones up to several GHz, IIRC, without too much amplitude loss. You just need to stay away from the sinc nulls.

-- john, KE5FX

It's deviation and minimum modulation frequency that set the maximum phase deviation. Conditioned, of course, by the preemphasis and spectral content of the signal.

HOWEVER: if the phase wraps, that doesn't matter -- as long as you deal with phase wrapping correctly, you're OK.

Well, as long as you _and the DDS chip_ deal with phase wrapping correctly...

I just got this nice DDS board, ADF4351 from Ebay, $33:

What's the 30000ft reason behind that statement?

That is not a DDS, it is a fractional-N synthesizer.

Well, maybe it can do what we want, when the dividers can be quickly re-programmed to do the modulation.

I'll also have to research if this method could provide a cleaner signal than a real DDS. I have also seen designs that use a DDS to generate the desired frequency, then follow it by a PLL to clean it.

However, my gut feeling is that using a fractional divider will result in terrible phase noise.

These chips are mainly intended to provide clock to digital circuits, where phase noise is not that much of an issue. I want to use it in a transmitter in a repeater. Closeby spurious should be in the

-60 to -80 dBc area and at 1.6 MHz spacing it should be well below

-100dBc. In this bandwidth that is about -140dBc/Hz.

Maybe I'll measure the phase noise, I have an HP3048A Phase noise test set. I have YIG osc that extremely quit, >-105dbc @ 10hz. As I recall, divide down the freq and you divide down the phase noise also. We once used an HP8662(?) and divided down to get a very stable clock for an A/D in a radar system.

Suggestion: use a cheap fractional-N synthesizer chip to make your 430 MHz. Varicap modulate the XO reference.