Yes. Old technique, in the 70s triangle to sine. For the vast bulk of modern applications, sine waves are not enquired. Standard precision xtal oscillators typically have cmos output, or what is referred to as "clipped sine". This latter is a misnomer though. In practice, its just a regulated slowish edged square wave. A key feature of the regulated output is much better PS rejection to frequency.
There is a parasitic capacitance from output to oscillator tank input. This forms a feedback miller capacitor. In a rail to rail output, the effective gain of that feedback is a function of the ps voltage, thus the capacitance changes, and thus changes the frequency. A few 10s fF is enough to cause a problem. Interestingly, with divide by 2, the cap variation goes away. It averages out. This can all be verified in a simple spice simulation as well as on the bench.
That idea was bounded about. Didn't take it any further. Can't remember why not.
It has very good specs and is certainly an interesting topology. I can't say I understand why it would achieve a better specification than a two stage at this point in time. I will have to do a detailed apples for apples comparison.
On the surface it appears to violate a well known result. That is, for given GBW, at the same power and accuracy it is better to spread the gain over several stages. The typical example being optimising the size of cmos inverters by increasing the size by e (2.7) at (load) each gain stage. For an op-amp 3 stages has extra stability problems that in practice make it not optimum, but for a two stage, its not immediately obvious why a single stage (a physical diff input followed by a cascade is still one gain stage) with gain at the 130dB level, would result in more optimum performance.
Its a neat trick to bootstap the output resistance of the gain stage transistor Q6 to get the gain up though.
My guess at the moment is that this topology doesn't achieve the maximum BW (with suitable compensation), for the supply current that could be achieved with the Fts of the process. Its just a basic result from the GBW of a stage being ultimately set by the devices. Two lower gain stages, cascaded, should always achieve a higher GBW.
I can't say I agree with the claim of "distortion cancelation" of the output stage. An amp with 110,000 loop gain at 1kH is going to have low distortion, period.
Off hand, if one had no Cc, there would be an almost standard Miller compensation using Cn instead. Now... move Cn to the input of the unity gain output buffer.
I have previously done a lot of simulations on including and not including the output buffer with the comp capacitor and always get the same distortion for either condition. The basic reason for this that for the comp cap on the input to the buffer, the buffer is driven by a low impedance. This means the gain is comp cap linearized at the gain point B, fed into a fairly good follower. If the comp cap is connected to the buffer output, the gain stage is now highly nonlinear because it is no longer feedback controlled by the comp cap. Additionally, its output impedance is high and all over the place so the follower is going to give large interactions with the gain stage, causing gross distortion. The total amount of distortion reducing feedback gain is the same in either case.
Usually, there is no such thing as a free lunch. My bet is that in this topology, simply moving that cap before and after the output buffer, won't make a difference to the distortion.
If I get time, I will will see if my conjecture holds up. I need to squeeze it in with my other hobbies:
Oh yeah... I did add a HF differential oscillator example to my SS download for 1 Jan 2019.
OscDiff2G5.sss
-- Kevin Aylward