Help with noisy HV supply

This application is for an analogue synth: it uses a 555 based clock and a 4017 counter to cycle through a set of voltage levels which are set by pots. The unusual aspect is that it displays the step of the sequence on a Nixie tube. A separate circuit is used to generate the

180V for the Nixie, and the digits are switched by MJE340 transistors. The HV supply is on a separate board from the sequencer itself.

The circuit diagram is here:

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(I "designed" this myself, and am by no means an expert - so please be gentle.)

The problem I have is (not surprisingly) voltage spikes on from the HV supply appearing on the output of the sequencer.

This set of scope traces shows, at the top, the HV supply (20V/cm,

2mSec/div) and on the bottom the sequencer output with the clock disabled (0.1V/cm, 2mSec/div).

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I seem to have about 150mV of spikes on the output :-(

Things I have tried: decoupling the HV board +9V supply rail from the sequencer board by a 100 Ohm resistor, and various smoothing capacitors across the 180V supply ... with very little success.

I'd welcome some suggestions on how to reduce the interference. I did wonder about using some optocouplers I have lying around, but maybe that's a bit far-fetched?!

Thanks, Julian

Reply to
Julian Bunn
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Is this on a proto board, a PCB, or some other construction technique? Can you post a picture of the layout? Problems like this are usually caused by poor grounding and/or decoupling. There don't seem to be any decoupling caps in the circuit as shown. As a minimum I'd add a 470uF electrolytic where the +9V comes onto the board, plus a ceramic 330nF directly across the supply pins of each chip. Also I'd route the supply and GND connections to the HV generator separately from those to the sequencer.

One other observation:

There doesn't seem to be anything to limit the flyback voltage on the collector of Q1. I'd measure the peak voltage with the scope and check it against the specs in the datasheet. In the absence of any snubber, the flyback voltage is only limited by stray capacitance. This is likely to destroy the transistor in the long term.

HTH

R.

Reply to
<news

The cause of the problem appears to be simple: these spikes occur when the transistor is switched off, and the transformer's reactance attempts to keep the current flowing, potentially leading to severe voltage spikes at the collector. This gets worse if the transformer has only a small secondary load. Now the TIP120 has a built-in reverse c-e diode, which has probably saved the transistor from being fried, but it also conducted the spikes onto the

+9V supply rail. A single 100 Ohm resistor won't do much good in that case, because it's primarily a current-driven spike. Including a capacitor (100-470uF) after the 100 Ohm resistor across the HV board supply rail should already improve things, but the best solution is to prevent these spikes from building up altogether, i.e. set up a proper damper (a.k.a. snubber) network on the primary side of the transformer. You may want to draw some inspiration from TV schematics, and in particular the SMPS primary side. This would seem a good starting point:
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Isolating part of the circuit using opto-couplers can help, but it's only treating the symptoms, not the cause of the problem.

Anyway, I hope this helps,

Best regards,

Richard Rasker

--
http://www.linetec.nl
Reply to
Richard Rasker

The counter analog voltage output is directly related to the 9V supply. If this dips or spikes, it will show up on Vout.

The big supply dip occurs when the HV oscillator turns on Q1, ramping up the transformer current.

Add local decoupling on the logic supply, isolated from the 9V with a resistor (100R, 10uF + 0.1uF) and add decoupling to the 9V supply directly at the HV oscillator (>100uF).

RL

Reply to
legg

My bet is that the 9V rail is being pulled down (out of regulation) due to the peak current.

Cheers, John

Reply to
John KD5YI

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e,

Thanks to everyone for the useful input. I am first going to try a snubber circuit on the HV supply Q1. I found some instructions for calculating suitable values here:

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Responding to a comment from legg (RL): how should I best make the counter voltage output immune to fluctuations in the supply?

Again, thanks.

Julian

Reply to
Julian Bunn

point:

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Others have commented on the 9V line - add a 470 uf electrolytic, isolate with 100 ohms, bypass with a small cap, all of which help to reduce fluctuations on it. In addition, use a voltage regulator to keep the line at +9.

Another technique to isolate Vcc: run the 9v supply directly to the transformer, and through a diode to supply Vcc to the 4017 & 555's. Connect a big electrolytic from Vcc to ground.

+9 ----+----- |a [D1] | +--- Vcc | [470uf] | Gnd ---+

Note that if regulation on the 9V line is shabby, you have to fix that first.

Ed

Reply to
ehsjr

point:

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The counter's voltage output cannot be immune to fluctuations in it's own supply, as the output is supply-dependent; that's how most cmos digital circuits are constructed. You could clip the output voltage to a level lower than any supply dip or regulate the supply voltage to a value lower than the bulk supply, independently.

Alternately, you could switch regulated currents rather than supply-regulated voltages, into your summimg node, at the expense of complexity.

You also might use multiplexer rather than a counter, to switch a regulated reference voltage or current, within the compliance of the multiplexer's internal analog switches.

You are performing the rough functions of a DAC - you might input your digital signals into an integrated DAC, with reference.

RL

Reply to
legg

Without looking at the other responses, i betcha that it you lifted pin 3 or pin 4 of TR1 that you would see the same problem.

Reply to
Robert Baer

point:

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Do not run the counter directly from the 9V supply; in fact isolate the 555 in the same manner; at least use a dropping resistor and zener to give a (say) 5V supply to them..and add a bypass cap. Make sure zener current is within nominal spec so that it does not oscillate(!).

Reply to
Robert Baer

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This improved things significantly. I did try adding a snubber to the transformer primary but it had little effect. The current schematic is here:

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I'm a little unsure about how I can reduce the spikes from Q1/TR1 further. I'd like to do more because other modules will also need to be attached to the

+9V supply, and I don't really want to be faced with filtering the spikes out for each of them :-)

Thanks again for the help from everyone!

Reply to
Julian Bunn

point:

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Your schematic shows that Vcc for IC3 is not isolated.

Feed +9 to the xformer. After that the 100 ohm and the diode. Like this:

+9 ---+---[100R]--->|---+---> Vcc for IC1, IC2 & IC3 | | [TR1] [470uf] | | Gnd---+-----------------+

You can probably omit the 100R. And you could add a .01 in paralell with the 470. Once all three IC's have their Vcc isolated you can look at snubbing across Q1.

Ed

Reply to
ehsjr

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Thanks Ed: this is great! Things look much cleaner now.

Reply to
Julian Bunn

point:

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Glad to hear that, Julian. :-) Did you have to add a snubber across Q1, or was it ok without it?

Ed

Reply to
ehsjr

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