Help on picking a part to use

I have outputs from 4 A/D's. Each output is 8 bits ( // output ) and will likely be sampled at 40MHz.

I need to manipulate that data in some kind of device. This includes level shifting, multiplying the data against each other and possibly applying some FIR filtering to the data. The output will be three 8 bit data streams running at the 40 MHz rate. Can anyone suggest a part to consider using for an application such as this?

Thanks.

Brent

Reply to
bulegoge
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An FPGA e.g. Xilinx Spartan-3.

Reply to
Andrew Holme

Xilinx Spartan3 FPGA. No sweat at 40 MHz. Exactly which one depends on how much math and buffering you need to do. Maybe you can quantify the requirements a little better and post to comp.arch.fpga, where people can suggest actual part numbers.

John

Reply to
John Larkin

I would suggest a small high speed sram with it, since he is doing FIR. It should cut down on the gate counts, unless cost is no concern.

Reply to
linnix

Depends on the size he needs. We're using an XC3S1500 in a couple of products, and it has 64 kbytes of block ram. The block ram is very fast and dual-ported, which is mighty handy, and you can partition it all sorts of ways. It costs about $67. An XC3S200 is more like $10.

FIR needs a lot of multipliers. We usually wind up using IIR filters.

John

Reply to
John Larkin

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Thanks everyone for the useful inputs

Reply to
bulegoge

I think you should go with the xc3sd3400a. It costs around the same as the xc3s1500 ($70) but same number of MAC (104) as the xc3s5000 ($120). As John said, you will likely be MAC bounded. For four inputs, you can do 25 TAPS FIR.

Reply to
linnix

Or if you work for the government, perhaps they can spare $8000 for the

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It gives you 176 MACs or 4 44 TAP FIR filters.

Reply to
linnix

How fast are those macs? With a multiplied 40 MHz clock, he could do multiple mac operations per "adc" clock, three or four at least, so effectively get more multipliers. In other words, run the filter math faster than the ADC rate.

One of my guys is a fan of boxcar averagers, which take very little resources and act sort of like lowpass filters. You can combine them with other-length boxcars, or simple IIR lowpasses, to zap some of the uglier sinc effects.

John

Reply to
John Larkin

I believe they are single cycle MAC. Xilinx's are 18 bits and Altera can be down to 9 bits. But a partial serial (4 TAPs per clock) design would be far more complicated than either a parallel or serial design.

The xc3sd3400a is going in the right direction, with more MACs and less gates. If only they can cut down the BGA pads (600+). I wish to have a thousand MACs in a 64 pins TQFP, less than $5 of course.

Reply to
linnix

16 bits in, 16 bits out, power, ground, clock. How about a DIP40?

John

Reply to
John Larkin

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Yes, 1.27mm pitch DIP40. I'll see if I can fit the 464 BGA in it. Don't forget jtags as well.

Reply to
linnix

I am not so sure about that if you have to off chip and back on, that takes a lot of cells also.

Reply to
JosephKK

Yes, simple sram wouldn't do it. We need multi-port register cells. But even with the top end chip, we are MAC bounded (100 to 200). So, the OP might end up with multi-chips with external registers anyway. We really need more info about his spec before making educated guesses. For example, are the transfer functions linearly independent on inputs? What is the order of the FIR filter?

The good news is that Spartan 3a dsp chips are surprisingly affordable. I though they were thousands of dollars before. Even a 5 chips solution (4 inputs + 1 mixer) would not be too expensive for a

45MHz dsp problem. We also need to know his budget limits, of course.
Reply to
linnix

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