help designing gimmick capacitor

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The old-tyme gimmick was two wires, twisted together. That would contain the field better than your open plates.

Another alternative: you could surround your cap with a shield and drive the shield from the FET source, bootstrapping it.

-- Cheers, James Arthur

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Hi James, The twisted pair may be the easiest, but as a thought, if I took a piece of coax and removed the center conductor leaving just the shield, then inserted a twisted pair as my capacitor. I then connect the shield the FET source, Ok, I have never bootstrapped before, but wouldn't I then have a higher potential than desired, even a possibility of oscillation? Mikek PS. Do I have any concern about inductive coupling with a twisted pair?

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That's too tight a box, and the dielectric screws things up--you'll be making shunt caps to the shield.

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Higher potential? No. Possibility of oscillation? Yes, but not likely. Keep the shield well clear of the gimmick to minimize that.

Just the twisted gimmick itself is probably all you'll need. The bootstrapping is lagniappe.

?

Nope.

-- Cheers, James Arthur

When you put the lid on, do you have a resonant cavity, and if so, what effect would this have ?.

You say 7dB down in gain, but at what frequency and is the response flat across the range ?...

Regards,

Chris

Use a real surface-mount 0.3 pF cap, or a homemade coaxial cap. The 1 cm square plates are too big and have their own capacitance to the world.

Bootstrap the drain of Q1.

"T" means transformer, which shows that this circuit was done by an amateur. All that tricky stuff could be replaced by one opamp.

It could have close to zero Cin with a little positive feedback.

John

Hi Chris, Not 7db, 7% down, if I have 0.8vpp output and I install the cover the output drops to 0.75vpp. I hope to have time this evening to try the twisted pair input capacitor. Your question is a good place add my next problem. The 3db bandwidth is 2.8 khz to 6 Mhz this is fine for my purpose but the designer says the response is over 10 Mhz. It looks like the drop starts at the source of the FET. Could that be the roll off of the 20 Meg and capacitance of the FET gate and capacitance to ground? I'll check response after I get the twisted pair put in. Thanks, Mikek

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For that matter the tiny input cap in Mike's circuit is counterproductive--it divides the signal down and makes the gain unpredictable.

Better: use 10pF coupling, lose less at the input, and use less gain later. Bootstrap the FET so the input sees very low C. Do those and you don't even need a gimmick.

I like the one at the top of pg. 2:

1970--a classic.

-- Cheers, James Arthur

John has mentioned plate size. Perhaps better to use a short length of thin semi rigid coax. Centre wire to input and outer shield to gate. Neater than a gimmick cap and easier to set the value before soldering into place.

Second stage loading ?. What happens if you scope T1 source with the second stage 100nF disconnected ?.

Forget the cavity idea - at 6 Mhz, I obviously wasn't paying attention :-)...

Regards,

Chris

Warning!

The 2N3644 is a PNP. The app note probably meant some other type number similar to that in an NPN.

Cheers, John

Ever consider simply using a proper air core variable cap?

One gotcha: with +12 on the drain of the jfet, expect a lot of gate current. Hot carriers or some such.

If the jfet drives a non-inverting opamp with gain, one could over-bootstrap the drain to hit zero or even negative input capacitance; tweak that with a pot or a small variable cap. Then, as you say, dump the 0.3 pF input cap and have predictable gain.

Phil Hobbs likes this:

+-----------+-----Vcc | | | | | R | | c | b----+-----+ < ~~ +3V e | | | | | | | | d C R in----------g | | s | | | | gnd | | +-----+-----------out | | | R < or current sink | | | Vee

John

Ah, he's done some nice work on the subject of crystal radios and high Q inductors.

Page down to experiment with LC circuits.

How much closer? If the input cap is 0.3pf what do you the input impedance is? Input is 0.3pf, 20 Meg to ground driving FET gate. Thanks, Mikek

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Good catch. The follower can be most anything, but not PNP!

-- Cheers, James Arthur

You have any 0.3pf air variables. Why is this one improper? Mikek

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s, Mikek

We're talking about something roughly like this:

+12V >-o-----o-----------. | | | | | | | | R5 3.3M | |Q2 | | \| | V1 | |---o-----o

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nks, Mikek

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Oh, I didn't calculate the biasing, so R4's probably wrong.

--James

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It's not so inpredictable, I set the amplifier gain at 17 and then adjusted the capacitor spacing for a total amplifier gain of 1. I'm not being argumentive, just trying understand.

I need to know more about bootstraping. Also doesn't the 0.3pf cap reduce the loading effect of the 20 Meg resistor? Thanks, Mikek

amdx Inscribed thus:

Change to a co-axial cap.

--
Best Regards:
                          Baron.

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The input gain of the original circuit depends on the voltage divider comprising your gimmick cap, on the one hand, and the FET's capacitance on the other.

No two FETs will have the same capacitance, so you can't know in advance exactly what the circuit's gain will be. That's why you have to tweak it via the input capacitor right now.

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Not really. At 1MHz, 0.3pf has a reactance of 530K, so it just adds

530K in series with 20M. It also attenuates your signal by a factor of 17, if the writeup is accurate.

The author says the amp's input capacitance is 1.4pF. That means either there's a lot of stray capacitance, or the input coupling cap is actually a lot larger than 0.3pF.

--James