I've got a simple op-amp circuit that is misbehaving in an EMI environment. It looks like below (hopefully the ascii drawings work out)...
___10k_______ | | GND--------|\\ 20k | \\____|___
--100----------|+/ |/
The numbers are resistor values and the + input comes from a unity gain buffer.
On first inspection my first obvious thought was to limit the bandwidth to avoid EMI issues (circuit only actually needs kHz'ish bandwidth) so I put a simple RC filter on the input as follows:
___10k_______ | | GND--------|\\ 20k | \\____|___
--100----------|+/ | |/ 1u = | GND
But this still had EMI issues and was probably bad because hanging a 1 uF cap off the input is a bad idea? Not that I have any fundamental basis for making that statement.
Consulting an EMC design book which has been *extremely* helpful in the past (EMC for Product Designers by Tim Williams), one of the things it recommends is putting low value resistors at each of the inputs, right at the pins. It also indicates that the values should be no larger than a few hundred Ohms. ie: adding 200 Ohms to each pin of the circuit above:
___10k_______ | | GND----200-|\\ 20k | \\____|___
--100------200-|+/ | |/ 1u = | GND
I'd like to understand what is going on here. My questions are:
- Is hanging a large capacitance on the input of an op-amp a bad idea? If so, why? I saw some rumblings somewhere about CMRR issues, but don't get it.
- With the op-amp having a high input impedance, what is the reason for limiting the resistors at the input pins to "up to a few hundred Ohms"?
I'm trying to simulate the impact of it all in Switchercad, but I'm a hack and my attempts have not been that illuminating. I've spent some time trying to work out how to simulate and understand when an amplifier circuit is stable or not, but haven't been able to fully grasp phase margin and certainly not how to simulate it properly.
Any help is much appreciated! I have an extreme dislike for doing anything because "that's just how you do it" and want to understand what is going on underneath.
Russ