goofy PWM

I need an isolated analog output (many of them, actually) with, say, 1 PPM programmability and linearity. An optocoupled DAC would be silly, so I'll use PWM.

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If I start at 200 MHz, and do a 20 bit (1 PPM) pwm, the output frequency would be 200 Hz. If I use a 3-pole lowpass filter (not too much delay) it has to be -3 dB at 2 Hz to get the ripple down to 1 PPM. That's the n-squared dilemma of straight PWM.

(Delta-sigma is noisy and has a lot of squirmy transitions. The average value will be disturbed by the rise and fall times of the optocoupler (or whatever) so getting to 1 PPM linearity is scary.)

To make, say, 20% output, PWM would be (in decimal) 200000 clocks high and 800000 clocks low. The ripple is 200 Hz.

But we could break the 5 msec PWM interval into four chunks, 50000 ticks high each, with the 800000 lows spread out between. That raises the ripple frequency to 800 Hz, and the filter bandwidth can go up to

8 Hz to maintain the 1 PPM ripple. Less delay.

To increase the straight PWM output by 1 PPM, the ON time would increase to 200001 ticks. In the boogered version, we'd generate

50001, 50000, 50000, and 50000 highs.

200002 would translate to pulse widths of 50001, 50000, 50001 and

50000 clocks. That balances the ripple.

Turns out there's an appnote a lot like this.

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An 8-fold booger is shown in Table 6. That would be nice, push my ripple frequency up to 1600 Hz. There seems to be no resolution or linearity penalty as long as I stay away from 0 and 100% duty cycle.

ST was trying to get more resolution out of a fixed-length PWM generator. In my FPGA, I can make any width PWM machine, but the trick is used to push the ripple frequency up.

Unlike true delta-sigma or PWM with a delta-sigma LSB dithering scheme, this is totally deterministic, hence noise-free, excepting the ripple.

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 
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John Larkin
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Check out

Sloman A.W., Buggs P., Molloy J., and Stewart D. "A microcontroller-based d river to stabilise the temperature of an optical stage to 1mK in the range

4C to 38C, using a Peltier heat pump and a thermistor sensor" Measurement S cience and Technology, 7 1653-64 (1996)

I think I've sent you a copy - e-mail me if you can't find it.

It describes a dead simple technique for decreasing the worst case ripple o n a PWM output. What it costs you is extra on-off transitions, which - if r ise and fall times aren't equal - add to your non-linearity.

Basically, if you generate your PWM waveform by using a digital magnitude c omparator to compare a fixed number - your PWM mark-to-period ratio - to th e output of a counter, comparing from most-significant bit down to least si gnificant bit minimises the number of transitions on the PWM output, while flipping from big-endian to little-endian on one or other maximiises the nu mber of transitions. If you don't want too many transitions, just scramble the high order outputs from the counter. I swapped the top four, pushing my maximum transition rate from 17.4kHz to 278.4kHz which was the point at wh ich my switching transistors started to run hotter. John could reverse the top twelve of his counter outputs before he hit 200kHz, and modern transist ors can be switched faster before the switching losses get bigger than the static dissipation when "on".

Delta-sigma isn't "noisy". It pushes the switching noise up to higher frequ encies, and introduces even more extra transitions than my approach - none of which are "squirmy" - whatever that might mean in this context.

There are more sources of potential linearity error at the 1ppm level than just differences between rise and fall times.

Not precisely. You still have to cope with the situation where one chunk is high for only 49999 ticks, while the others are high for 50000 ticks.

That's a 200Hz component, but you can organise things so that the worst cas e 200Hz component is a quarter the size it was with the simple minded appro ach. Check out my paper - it's spelled out there for 16 chunks, and the wor st case over-all repetition rate component was then reduced by a factor of

It's dated 2014, My paper is dated 1996 and I've talked about the approach here once or twice.

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Bill Sloman, Sydney
Reply to
Bill Sloman

It's actually the overall ON vs OFF delay times, rather than rise time alone. The on vs off delays are often quite different for optical-couplers and drivers, but they're generally fairly stable and repeatable. It'd be easy to add adjustable fixed delays to both the on and off times, so they could be trimmed to be more or less the same. I'll bet a given choice of components in a production run would have pretty closely matched delays; measure one and apply the delay components to the rest.

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 Thanks, 
    - Win
Reply to
Winfield Hill

Yeah, the bottom line problem with D-S is on/off asymmetry, which makes errors at high, and essentially random, pulse rates. But I wouldn't want to attempt to tune it out.

1 0 1 0 has 8 edges, whereas 1 1 0 0 has only 4, so they won't average the same. Delta-sigma generates too many cases. The IC boys must do tricks to make D-S ICs as good as they are.

The clustered/boogered PWM always has the same, small number of edges, so will always be monotonic and noise-free.

It's really not worth trying to de-cluster the wider pulses, ie

50001 50000 50001 50000 ON versus 50001 50001 50000 50000

since the difference in ripple is a couple PPMs, and the lowpass filter will kill that tiny residual ripple.

There probably *is* some tricky math algorithm to evenly disperse the N+1 pulses, some bit-field reversal or something, sort of a Van der Corput sequence thing. My guys will get into that math fun, even if it's unnecessary.

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John Larkin         Highland Technology, Inc 
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John Larkin

Reversing the order of the most significant bits of your counter output does it automatically - no math fun involved.

But you should have known that ...

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Bill Sloman, Sydney
Reply to
Bill Sloman

You can use rational approximation to approach an arbitrary idealized ratio.

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Iterate until the denominator is greater than the maximum count length of the register (i.e., 65536 for a 16-bit register; maybe you'd be limited by output frequency instead for longer registers). Stop and take the preceeding pair.

While you're at it, check the ordinary N/MAXCOUNT ratio and see if it's better. If so, pick it.

As with D-S, the worst case ratio need not be any better than the ordinary step size of the PWM register. Indeed, this method is constructing the sum of a D-S sequence, analytically rather than by feedback and time.

The results can be much better than N/MAXCOUNT in the general case. (Which is more important, RMS or peak INL/DNL?)

You can also calculate step sizes by varying the denominator, as you propose: a / (b + epsilon) ~= (a - epsilon/b) / b

If you use this as a repeated increment to the register values, you'll want to also apply some "negative feedback", such as a few iterations of Newton's Method of approximating a function (perform that approximation with extended precision, then truncate the fractions when complete, don't just iterate on the integers).

Tim

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Tim Williams

Also, were you expecting anywhere near 0% or 100% duty? Obviously that's a problem for optos. You'll have to subtract some amount from each end (10-90% working range?), magnifying the juicy middle, and making it that much more critical to be linear and all that.

Tim

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Tim Williams

I'm willing to avoid small zones around 0 and 100%.

In fact, I'll be using a commercial, isolated, 24-bit delta-sigma ADC to feed back the actual output voltage; we have some good reasons to do that. But the ADC will be slow, so the PWM DAC not only needs to be monotonic and quiet to 1 PPM, it needs to settle reasonably fast, so we can close the loop nicely.

Having a very linear DAC is good, too. Once we know the DAC slope and offset, easily measured at powerup, the convergence algorithm can really rock.

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John Larkin         Highland Technology, Inc 
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John Larkin

Rather than PWMing the whole thing and dealing with the issues, it can be done easily with a multiple DAC which can also be dithered to get the resolution you need.

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8 channels in one chip and one interface. Update at X times per second and Bob's your uncle. You might even be able to eliminate the ADC.
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Rick
Reply to
rickman

1 ppm linearity might be a bit of a challenge, though.

Cheers

Phil Hobbs

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Phil Hobbs

Right. Delta-sigma ADCs are astonishing. There's nothing that you can afford that's anywhere close to as accurate and linear as they are.

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John Larkin         Highland Technology, Inc 
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Reply to
John Larkin

So what's so bad about a DS DAC? They can be had at up to 24 bits.

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Rick
Reply to
rickman

Got any parts in mind? I need DC accuracy, and audio parts don't generally guarantee that.

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John Larkin         Highland Technology, Inc 
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John Larkin

??? I count 4 and and 2 not 8 and 4

pure bit field reversal gives an effect a bit like a delta-sigma, most of the noise goes into the high frequencies but the number of transitions is variable. burkes dither used to convert photos one bit depth works like that.

If you want a fixed number of transitions

pick how many sub-fields you want in your modified PWM and then shift your counter output log_2 that many bits leftwards, reverse the order of the bits that overflowed and insert them into the vacated spots on the right,

so for an n bit counter to be split into 8

n n-3 n-1 .... n-2 ----\ 3 n-3 \ 2 ... / 1 3 -----/ 0 2 n-2 1 n-1 0 n

if the counter isn't a full binaary counter or you need a number of fields not a power of two, you'll have to use some other base,

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umop apisdn
Reply to
Jasen Betts

Whatever scheme you pick, you'd like to keep the total transitions/sec reasonably low, and the minimum transition period fairly long, much longer than ON and OFF time-delay differences.

This means you can trim the delay times as needed, and easily pick up a 5-10x linearity improvement. I wouldn't call that tuning.

--
 Thanks, 
    - Win
Reply to
Winfield Hill

My scheme was to reverse just the top four bits of the 10-bit counter output

Counter Comparator

6 \ 10 7 \ 9 8 \ 8 9 / 7 10 / 6 5 5 4 4 3 3 2 2 1 1

which gave 16x more transitions, and a well defined maximum transition rate.

John could presumably reverse the order of the top ten of his counter outputs for 1024 more transitions and the same maximum - 200kHz transition rate.

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Bill Sloman, Sydney
Reply to
Bill Sloman

How would I trim the delay times?

With plain or goofy PWM, there are only a few transitions per cycle, and any rise/fall asymmetry becomes a small, constant DC offset, independent of output value. My system will dynamically cal out any DC offset. Pulse width distortion shouldn't affect linearity.

I'd probably use one of the ADUM1401A family of isolators. Pulse width distortion is 40 ns max, and 11 ps/degC typ.

200 MHz, 1e6 counts, 4 goofies per cycle, is an 800 Hz pulse train. The 40 ns delay distortion will add a tiny offset, way below what I'll see from opamps and such. I think it will work.

I will have to test those ADUM parts for jitter. It's not actually specified. We stock the "A" grade parts, but the "B"s have lower PW distortion specs.

TI has some nice isolators, 2.5 ns max PW distortion.

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 
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John Larkin

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working out how you'd find out what changes to make might be more difficult , but I've worked out schemes.

With "goofy" - reduced ripple - PWM the number of transitions per cycle var ies so the error ceases to be a DC offset. My scheme limited the number of transitions in my output to equal to or less than about 16 per cycle. If on e applied something similar to your application you could have anything fro m two to 1024, through mostly you'd have 1024 - in the range from 0.1% to 9

9.9% of full scale.

That doesn't take into account the differing rise and fall times on the swi tches doing the actual pulse width modulation, which does matter.

If you just want precise isolation, a three-winding transformer can be diff icult to beat - one high current winding is driven, one on the driven side is used to sense the rate of change of flux in the core as a voltage, and t he third isolated winding on the other side generates exactly the same volt age - if it's wound bifilar with the other sense winding - to about one par t in 10 million.

There's a upper limit to the frequencies you can push across with that prec ision, but it beats the pants off 200Hz PWM.

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Bill Sloman, Sydney
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Bill Sloman

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It does have a guaranteed bipolar zero error at +/-2% of full scale, which isn't impressive for a 24-bit part. The +/-0.5% typical range isn't impressive either, but there is at least "a" guaranteed specification.

Burr-Brown originally aimed the part at instrumentation applications as well as audio, and it shows in the data sheet.

If you did your "goofy" PWM properly, you could do a lot better.

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Bill Sloman, Sydney
Reply to
Bill Sloman

I was diagramming the transformation to make to the clock my second column is the order the go into the comparitor

that looks like it would give mismatched pulse lengths: most of the of the 32 slices would be either full or empty.

What I have done is reverse all the bits which gives maximum deterministic dither at the cost of an umpredictable number of edges per cycle, but then un-reverse the least-signifigant bits to limit the number of edges. so long as he programme input stays in the middle of of its range (does fill or empty all its high-order bits there will be a predictable number of transitions (2^(b+1)) for b bits moved.

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umop apisdn
Reply to
Jasen Betts

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