Good Find, CD4007 Spice Model Library....

I think you can go 5 volts to 15 volts level conversion with a 4007 and zero external parts, but the power dissipation would be nasty.

One resistor, easy.

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John Larkin         Highland Technology, Inc 

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John Larkin
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Show us. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Jim Thompson

Good! Maybe then LT parts would be cost-competitive! ;-)

(Reminder what you're referring to: LTSpice is a marketing tool, and as such, its development cost is rolled into the bottom line of _every part purchased_. Strictly speaking, parts would be cheaper without LTSpice. Presumably, they would get fewer design wins and therefore lower revenue if they dropped it, so LTSpice carries on.)

Tim

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Tim Williams

The single-resistor+single-4007 thing is trivial, and adding hysteresis with one more resistor should be obvious. The trick would be to do it with no resistors, working with the 4007 pinout.

This could work:

formatting link

the trick being to get the first-stage pullup current down to some sane value. This circuit might work with 5V input, probably not at

3.3.

Of course, there are better ways to do this function.

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John Larkin         Highland Technology, Inc 

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John Larkin

I posted the Spice Model... show us that your scheme works.

Yes. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Jim Thompson

In the CD4007 some of the sources are not connected to their substrate so TGs become possible. How about in your circuit driving one of your input pmos gates from the output instead of the input?

piglet

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Piglet

No reason to do that. Too much work, and it's not my problem.

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John Larkin         Highland Technology, Inc 

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John Larkin

With Dr. Fuller's permission, it is now also posted on the Device Models & Subcircuits Page of my website. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Jim Thompson

If the TTL world provides complementary true and true-bar inputs to the level shifter then 2/3 of CD4007 can shift to high level very easily:

If there are inverters or other CD4007s living in the low rail environment they could provide the low-level inversion.

Real shame all the CD4007 p-channels are tied to Vdd - then this challenge would be simpler :>

piglet

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piglet
[snip]

That is the classic way that level-shifting is done on-chip (with embellishments that minimize the peak current required at each transition).

First thing I tried. The problem is that the N-channel devices are too 'weak' to overcome the P-channels, thus I went the route of the added resistors.

Only the body ties are to VDD, two of the P-channel devices have free sources.

I'd would have loved to have a few 'free' N-channel gates, then my embellishment tricks could be implemented.

On custom chip designs I have all those freedoms plus I can size devices at will ;-)

(I think it was you, piglet, who commented, "...power from output" for the first inverter. That's also in my bag of tricks, but also wouldn't play because the N-channels at three volt gate drive are 'weenies' ;-) ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Jim Thompson

Why not a single grounded-source n-fet, and a pullup resistor on the drain?

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John Larkin         Highland Technology, Inc 
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John Larkin

If your application can tolerate the exponential rising edge, sure, why not.

The 'classic' approach in CMOS has quite 'stiff' edges at the output (there _is_ positive feedback, two inverters tied back on themselves). ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Jim Thompson

After the nfet input stage, there are two leftover buffers in the

4007. It's easy to make a Schmitt, too.
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John Larkin         Highland Technology, Inc 
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[snip]

One embellishment method...

Done by ignoring the pin-out restrictions of the CD4007 but no optimizing size scaling. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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Jim Thompson

That's an example of Leaver's Law. Putting many transistors into an integrated circuit is a big win. But, everything it does FOR you, it also does TO you.

SOS (silicon-on-sapphire) and other oxide isolation gets around this, but adds cost and complication.

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whit3rd

adds cost and complication.

SOS was an '80s enthusiasm, mostly of HP's, iirc. More modern S0I is a whole lot cheaper--a bonded or SIMOX wafer isn't that much more expensive than a bulk wafer.

There are still a few folks using SoS, but it's far from mainstream.

Cheers

Phil Hobbs

Reply to
pcdhobbs

Thanks Jim. That embellishment is too subtle for me: MN1 and MN2 have their gates at +15V and their substrates at 0V so both will be fully enhanced and basically just two pieces of wire. Is that a monolithic way of making a low resistance?

piglet

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piglet

Yeah, but that is a real-world way of doing things :>

The more interesting problem was to make it true to the ethos of CMOS and have no current draw for either logical state.

piglet

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piglet

Don't cheat by requiring complementary TTL inputs!

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John Larkin         Highland Technology, Inc 

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At the low end of the output swing they're low resistances, at the high end of the output swing they're high resistances. Thus the low current required to 'upset' the latch. ...Jim Thompson

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| James E.Thompson                                 |    mens     | 
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