In addition to (AD9838 style) things with DAC outputs, there are PLL solutions to the make-me-a-frequency-to-order problem. Basically, start with a reference oscillator (F_ref) and divide it by a counter-based logic (which gets F_ref / N_one), and phase-lock to a voltage-controlled oscillator F_vco, with its own divider
F_ref/N_one = F_vco/N_two
There are reasons to prefer that both N_one and N_two be even numbers (last stage is a divide-by-two so you get 50% duty cycle square waves). There's still a large candidate pool of N_one and N_two values, though.
So, if you wanted to trim the frequency up a few parts per million, how do you select the new N values? If there's ten bits in the counters, there's a million ( 2**20) candidates to check to find the best one...
The only simplification I see, is that one can make a rank 2**10 matrix of the combinations, and note that the equation we want amounts to:
F_ref * N_two = F_vco * N_one
which is the equation of a straight line in the N_one, N_two coordinate system, going through (0,0) (which are NOT divisors, you just have to disallow the divide-by-zero "solution").
There's a well-known algorithm for drawing the best line in such a two-dimensional array, the Bresenham line-drawing algorithm, so it's a little better than 2**20 cases to consider; more like 2**10 points that 'fit' that line equation nearly.
Still, its a bit tedious to brute-force search for the best-match ratio; is there a better way? And, how does one extend the scheme if there are fractional-N tricks (pulse swallowing, basically) used for fine tuning?