Free/Open Source PCB autorouter in development; help wanted

Hi,

There are a few free/open source PCB autorouters available however using them has been quite difficult due to a lack of interchange standards. There are at least three available such as MUCS-PCB, gEDA PCB (includes autorouter), and the Topological Autorouter (experimental also part of gEDA PCB).

The QAutorouter provides a solution of building the Specctra DSN import and SES export facilities and a common API for "plug in" autorouter engine modules.

Probably the best PCB autorouter for hobbyists at the moment is FreeRouting.net which supports Specctra DSN import and SES export. It is a very capable and effective PCB autorouter. The KiCAD, gEDA, FreePCB, and Eagle EDA tool sets all support Specctra DSN export and SES import and can use FreeRouting.net. However, while FreeRouting.net is free to use (as in beer) it is still commercial software so hobbyist support is limited in that the source code is not available.

A truly free/open source PCB autorouter has been needed by the hobbyist EDA community for quite some time. If you are skilled software developer and familiar with EDA this would be a great opportunity to help out. Thanks in advance for your time and have a nice day!

Andrew Lynch

PS, please see the original announcement on KiCAD-users mailing list.

Reply to
lynchaj
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All the times I've seen an autorouter used, it did horrible layouts. Between the extensive setup, and the extensive cleanup, they haven't been worth it. Besides, routing and designing pours is the fun part.

John

Reply to
John Larkin

Autorouters for chips work pretty well. There is still cleanup to do on critical nets but processors (or most FPGA designs) wouldn't be possible without auto-placement/routing. At the board level it seems they're of a lot less utility, perhaps because boards aren't "regular" and there is a lot to be gained by intuition. It could also be that there is a lot of the design that isn't stated in the schematic. I have a pretty good idea what a board should look like long before placement starts. The layout guy often seems to be in disagreement, though. ;-) He often doesn't even read the hints in the schematic ("layout notes"). :-(

Is that why you have the brat do it?

Reply to
krw

Big digital ICs probably wouldn't be possible without autorouting, but I bet there's a lot of human guidance involved, still. People are still best at strategy.

At the board level it seems they're of a lot

Placement is key to routability. And auto-placers are worse than auto-routers.

The layout guy often seems to be in

It's best to work in physical proximity to the layout person, and interact. "Oh, I forgot to tell you, those clock lines can't run near those output traces" or "flip that connector over, please." Our manufacturing people get consulted, too, before it's too late.

I lay out a small board now and then, but I just don't have the time to do serious boards. She just finished a laser controller that took about three weeks. I do take her boards home and check/tweak them, because I know stuff that she doesn't, or stuff we forgot to mention. I mostly look at impedances, terminations, bypassing, and look for obvious mistakes. I tweak the schematics for style, too.

I often do placement for tricky sections, like GHz stuff, and let her take over.

We did screw up one board recently. It had been extensively design reviewed, and two people, including me, checked the schematics and the layout. None of the power nets (+5, +12, -12, ground) were connected to pins on the VME connector.

John

Reply to
John Larkin

Sometimes auto-routers screw up at the last minute. I had on case, a switch-mode converter, go wrong. Client showed me the last layout, looked ok. But then they did one more minor change, let the autorouter run a few traces again, and didn't have me check it off because they were mere minutes away from the evening deadline for production. Sure enough it moved a bootstrap feed trace up top that absolutely should not be there. Turned it on, the inductor coupled spikes into the bootstrap trace, made the voltage exceed abs max ... *PHUT*

[...]
--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

The chips I worked on, most was autoplaced and routed with the hand stuff being done at the end to close timing. No need to mess with nets that worked.

Again, your experience is with boards. Chips, particularly digital ones, are a little different, though I suppose you could equate floorplanning with chip placement.

He's in the next office (but sometimes that's a world away).

That's what I like in engineering; style points. ;-)

We'll see how the board with the 13 AMD iso-power (180-300MHz) thingies came out. It's back from fab but manufacturing has been busy with that icky stuff that people pay for. I may take it up to Atlanta to have a pre-scan done.

BTDT. Our layout guy is always screwing up the footprints so we check them pretty thoroughly, though it just bit us again on a prototype/production test board. He got the pushbuttons on sideways. "It's just a test board."

Reply to
krw

100% routed by hand by me:

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I wish there was a good autorouter to do that intead though as it really took a lot of work. I wish your qautorouter project success, autorouters could use a lot of improvement from what I've seen.

cheers, Jamie

Reply to
Jamie

Hi!

Can't you benefit from the bus hints, chip-info and crystals, deduce which connections are:

  • high/low-ohmic
  • high/low current
  • high/low frequency
  • connections that depend on delays on other connections - and not
  • (un)balanced connections
  • user hints, when needed e.g. (star-ground?)

and combination of the above? So e.g. high-ohmic are short and is not near high current/frequency connections? How hard can that be ;-)

To deduce or "limit" autoplace and autoroute?

-

Are we still doing stone-age AI? ;-)

Glenn

Reply to
Glenn

And why aren't we using asynchronous logic/circuits everywhere?

Why do still relay on a global clock - it sucks ;-)

It asks for glitches and to much power.

Asynchronous circuit:

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Quote: "... Benefits ...

  • Early completion of a circuit when it is known that the inputs which have not yet arrived are irrelevant.
  • 70% lower power consumption compared to synchronous design[3]
  • Possibly lower power consumption because no transistor ever transitions unless it is performing useful computation (clock gating in synchronous designs is an imperfect approximation of this ideal). Also, clock drivers can be removed which can significantly reduce power consumption.... ...
  • Better modularity and composability. ...
  • Far fewer assumptions about the manufacturing process are required (most assumptions are timing assumptions).
  • Circuit speed adapts to changing temperature and voltage conditions rather than being locked at the speed mandated by worst-case assumptions.
  • Immunity to transistor-to-transistor variability in the manufacturing process, which is one of the most serious problems facing the semiconductor industry as dies shrink.
  • Less severe electromagnetic interference (EMI). Synchronous circuits create a great deal of EMI in the frequency band at (or very near) their clock frequency and its harmonics; asynchronous circuits generate EMI patterns which are much more evenly spread across the spectrum.
  • In asynchronous circuits, local signaling eliminates the need for global synchronization which exploits some potential advantages in comparison with synchronous ones. They have shown potential specifications in low power consumption, design reuse, improved noise immunity and electromagnetic compatibility. Asynchronous circuits are more tolerant to process variations and external voltage fluctuations=E2=80=8E[1].
  • Less stress on the power distribution network. Synchronous circuits tend to draw a large amount of current right at the clock edge and shortly thereafter.... ... Disadvantages ..."

Asynchronous logic:

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2/8/2006, ARM offers first clockless processor core:
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Glenn

Reply to
Glenn

Because a reliable, robust, economical solution to asynchronous transitions apparently doesn't exist? What do I win?

It works.

Glitches can be dealt with and "to" much power is relative.

[Handwaving snipped]

Fabricated from unobtanium.

What is the unit cost of a ARM996HS-based processor?

The ARM Cortex M3 was introduced at about the same time as the clockless core touted above. Compare and contrast the number of units shipped.

--
Rich Webb     Norfolk, VA
Reply to
Rich Webb

Meta stable states?

Reply to
Raveninghorde

On 10 Jul., 13:07, Rich Webb wrote: ...

Hi Rich

I think SmartMX P5CD072 is asynchronous:

November 25, 2008, NXP Ships 100 millionth ePassport Chip:

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e-15030.html

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Quote: "... P5CC081UA Secure dual interface and contact PKI smart card controller ... low-power, performance optimized asynchronous technology. ..."

The International Symposium on Asynchronous Circuits and Systems (ASYNC):

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Quote: "... ASYNC 2012 will be co-located with the 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2012) ..."

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Alta: The 4th generation switch chip from Fulcrum Microsystems:

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Quote: "... Process and Power The FM4000 Series devices are implemented in TSMC=92s 130nm FSG process and consume less than 1.5 Watt per active 10G interface with typical traffic activity. Unused interfaces that are disabled consume no power, and power scales directly with the level of activity. ..."

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Proteus Automated Design of GHz Asynchronous Circuits:
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GHz Asynchronous SRAM in 65nm:
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I do not know for shure if this chip is genuinely Asynchronous:

June 2, 2011, Qualcomm=92s Dual-core is asynchronous, demonstrated at Computex 2011:

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trated-at-computex-2011/ Qualcomm's Dual-core is asynchronous, demonstrated at Computex 2011:
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MSM8660

Apr 2nd 2011, Qualcomm's 1.5GHz dual-core MSM8660 destroys the competition in majestic benchmark run:

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oys-the-competition-in/

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Video:

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true&iframe=3Dtrue

Glenn

Reply to
Glenn

Why in the world would you think that? Even a brief look at the datasheet reveals lots of discussion of clocks, CLOCKSTOP sleep modes, and tidbits like an architecture built around a "dedicated Secure_MX51 Smart Card CPU (Memory eXtended/enhanced 80C51)." 8051?!

"Asynchronous" isn't even mentioned in the datasheet.

Sorry. Looks like you're just a troll. Bye bye.

--
Rich Webb     Norfolk, VA
Reply to
Rich Webb

be

Nice. It shows a lot of strategy.

John

Reply to
John Larkin

Look at the list of implementations. Looks to me like zero are commercially available.

I read somewhere that parts of some x86 chips are/were async.

Imagine designing a nontrivial state machine with async logic.

Imagine simulating it.

I do occasional async logic, small stuff. My co-workers are horrified. But it doesn't scale.

John

Reply to
John Larkin

It appears that there are "asynchronous dual core" CPUs out there, but in this case the asynchrosity (?) relates to the ability to put the cores to sleep independently, rather than to a processor core built out of non-clocked combinatorial logic.

--
Rich Webb     Norfolk, VA
Reply to
Rich Webb

Imagine running a noise-sensitive system such as an ultrasound scanner if it had non-synchronous clocking. That would be horrid.

[...]
--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

I assume that the switching noise would sort of happen all over the place, vaguely spread-spectrum, but would of course follow any and all signal inputs. Nightmare.

Async logic is like multi-level logic, fuzzy logic, neural networks, and other recurrent fads. It might make sense as subsystems inside synchronous processes, like maybe a brutally parallel floating-point ALU.

John

Reply to
John Larkin

Yeah, what ever happened to fuzzy logic? 20-30 year ago it was all the rage, now not much is heard about it anymore.

--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

Domino logic is pretty common for such things. It's set up synchronously and sampled synchronously but in between it's dominoes. ;-)

Reply to
krw

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